|
发表于 2023-4-25 05:55:30
|
显示全部楼层
我算一下應該有機會
For example:
800KHz Fsw PCM Buck 2.5 - 5.5 to 1.8 Io < 1A, @T18BCDG3
Ls = 4.7uH, Co = 22uF MLCC x 2
FGD Vref Iq < 1uA
Feedback Res.: 220k - 500k iq,max = 1.8V/720k x (1.8/2.5) = 1.8uA
Design Ri = 1
Current Sense: 1: 100000 --> Max ~= 10uA,Common Gate Amp. ~= 10uA
Rcs = 100KOhm
Slope Comp. = Vo/Sf --> ~10uA, summing Slope comp. direct at CS --> DC shift current = 10uA
design BW = 1/10 Fsw = 80KHz, zero ~= 8kHz --> Cc ~= 100p, Rz ~= 200k
1 / (Rz x EA'Gm) = 1/2pi/80K/2/22uF = 0.045 -->EA'Gm = 1/0.045 / 200k ~= 11uA/V
EA Gm = 5.5uA/V --> Tail Current = 11uAV / 20 * 2 >= 1.1uA, folded cascode topology whole Iq ~= 5uA
Delay effect < -10d phase shift @ BW --> arg(exp(-j x 2pi x 80k x Td)) < -10d --> 0.34us
Modulator delay = 0.3us --> 3dB BW ~= 0.5MHz --> T18 5V pmos transistor ft @ minimum length ~= 0.8GHz
Iq ~= 20uA
到這邊大概45 - 47uA
ZCD, OCP, OVP... protection 加加減減 壓在75uA左右 (覽得算了) 還沒clamping
如果ZCD後DCM那段把current sense 關掉, 然後把 ZCD自動關掉, OCP也關掉壓進 45 - 50uA 在這個process應該很輕鬆
變頻懶的算了, COT 把EA關掉(0-Iq), ramp 用passive做 (0-Iq), FGD Vref < 1uA, CMP 不切 < 20uA, 其他ZC, Ton, Toff, 關光光, 不用特地做加速機制隨便都壓到50uA以下
|
|