为什么让generated clock的pin和 source 的pin是一个点？

jiaosir003

                               
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请问下面定义MUX输入端的生成时钟时，为什么让generated clock的pin和 source 的pin是一个点（红色标出部分）？既然是一个pin了还加个-combinational 干啥？

考虑到选择器之前各个时钟间有crosstalk，选择器之后没有crosstalk，所以声明如下：

Create_clock  -period  10 CLK

#####define divide_by_2，divide_by_4 clocks

Create_generated_clock  -name CLKdiv2  -divide_by_2  FFdiv2/Q  -source  FFdiv2/CK

Create_generated_clock  -name CLKdiv4  -divide_by_4  FFdiv4/Q  -source  FFdiv4/CK

#####create clocks arriving at MUX inputs

Create_generated_clock  -name CLK_mux  -combinational UMUX/A  -source UMUX/A

Create_generated_clock  -name CLKdiv2_mux  -combinational UMUX/B -source UMUX/B

Create_generated_clock  -name CLKdiv4_mux  -combinational UMUX/C -source UMUX/C

#####define clock at FFdiv3

Create_generated_clock  -name CLK_mux_div3  -divide_by 3 -source FFdiv3/CK  -master CLK_mux  -add

Create_generated_clock  -name CLKdiv2_mux_div3  -divide_by 3 -source FFdiv3/CK  -master CLKdiv2_mux  -add

Create_generated_clock  -name CLKdiv4_mux_div3  -divide_by 3 -source FFdiv3/CK  -master CLKdiv4_mux  -add

####apply physical exclusivity

Set_clock_groups  -physically_exclusive  

-group {CLK_mux  CLK_mux_div3}  \

-group {CLKdiv2_mux  CLKdiv2_mux_div3}  \

-group {CLKdiv4_mux  CLKdiv4_mux_div3}

simplo

When you create the generated clock using the -combinational option,  there must be a valid path for propagating the rise and fall edges of master clock to the generated clock source pin and the source latency paths for this type of generated clock only includes the logic where the master clock propagates

xingyun666666

simplo 发表于 2023-3-21 12:57
When you create the generated clock using the -combinational option,  there must be a valid path for ...

man了一下没太看懂，-combinational的意思是？

-combinational # Consider only combinational paths for latency (bool, optional)

jiaosir003

xingyun666666 发表于 2023-3-21 16:24
man了一下没太看懂，-combinational的意思是？

-combinational # Consider only combinational paths fo ...

就是 generated clock pin和他的source pin必须有组合逻辑关系

jiaosir003

jiaosir003 发表于 2023-3-24 11:03
就是 generated clock pin和他的source pin必须有组合逻辑关系

但是这个教程命令里把generated clock pin和他的source pin定义成了一个pin,所以不理解

jiaosir003

xingyun666666 发表于 2023-3-21 16:24
man了一下没太看懂，-combinational的意思是？

-combinational # Consider only combinational paths fo ...

但是这个教程命令里把generated clock pin和他的source pin定义成了一个pin,所以不理解

simplo

xingyun666666 发表于 2023-3-21 16:24
man了一下没太看懂，-combinational的意思是？

-combinational # Consider only combinational paths fo ...

Xilinx

-combinational:

The sourcelatency paths for this type of generated clock only include the logic where themaster clock propagates.

The sourcelatency paths do not flow through sequential element clock pins, transparentlatch data pins, or source pins of other generated clocks.

This optionis not intended to be used with logic that manipulates the clock, such as CMB(Clock Modifying Block).

-divide_by:

-divide_byarg - (Optional) Divide the period of the master clock by the specified valueto establish the period of the generated clock object.