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发表于 2023-7-17 22:51:47
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這個問題很深分開討論唄:
ckt 上面看起來就是多惹一個ZC而已但是
Constant Freuqency V-Mode control:
CCM: Error amp. to output voltage 看到 LC complex poles --> 看esr zero位置決定Type-II or III compensator
DCM: 因為控制D --> 控制 iL peak --> complex poles 解藕 成single poles --> copmensation好做 maybe Type-II only
又因為fixed frequency --> DCM D 正比於 Io --> ckt implementation 會遇到 cmp nonlinearity @ small Io, UG CS也會有settling time issue
Constant Frequency Peak Current Mode Control:
CCM: Vo/Vc = iL/Vc x Vo/iL = iL/Vc x Zo : 退化成VCCS single pole --> type II only but need slope comp. for D > 0.5 and for better noise immunity, 另外implementation上面還要做leading edge blanking 跟minimum on time
DCM: 此時slope comp.情況變的比較複雜一點~ 詳情請去看 fundamental of power electronics 那本書裡面有推導
至於如果去看ridley的model會發現 Q2 這個東西會影響到你的最大頻寬能推多少, 個家公司有各種adaptive ramp based on Q2 or falling slope 可能看一看paper跟patent大概可以知道再幹嘛
剩下的COT 那些就比較複雜惹, 涉及到EA output lower clamping, external ramp clamp 還有 outer loop 怎麼加進去, 可以多看paper跟patent
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