vcs仿真rtl代码，带-vera，仿真出现问题求教？？！

sanluht

最近在用vcs仿真代码时，内部使用了amba的vmt，vcs的option也增加了-vera，仿真出现以下问题，尝试了好多方法都没有解决，请大家帮忙看看，谢谢！以下是仿真打印log信息：
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv   -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  -rdynamic  /home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vera_user.o   amcQwB.o   _prev_archive_1.so _csrc0.so  SIM_l.o  _csrc0.so    rmapats_mop.o rmapats.o rmar.o  rmar_llvm_0_1.o rmar_llvm_0_0.o          /home/edatools/synopsys/vcs-mx_vL-2016.06/linux64/lib/libzerosoft_rt_stubs.so /home/edatools/synopsys/vcs-mx_vL-2016.06/linux64/lib/libvirsim.so /home/edatools/synopsys/vcs-mx_vL-2016.06/linux64/lib/liberrorinf.so /home/edatools/synopsys/vcs-mx_vL-2016.06/linux64/lib/libsnpsmalloc.so /home/edatools/synopsys/verdi_vL-2016.06-1/share/PLI/VCS/LINUX64/pli.a /home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a -lnsl    /home/edatools/synopsys/vcs-mx_vL-2016.06/linux64/lib/libvcsnew.so /home/edatools/synopsys/vcs-mx_vL-2016.06/linux64/lib/libsimprofile.so /home/edatools/synopsys/vcs-mx_vL-2016.06/linux64/lib/libuclinative.so   -Wl,-whole-archive /home/edatools/synopsys/vcs-mx_vL-2016.06/linux64/lib/libvcsucli.so -Wl,-no-whole-archive        _vcs_pli_stub_.o   /home/edatools/synopsys/vcs-mx_vL-2016.06/linux64/lib/vcs_save_restore_new.o -ldl -lm -rdynamic -ldl  -lc -lpthread -ldl
/home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a(vsv.o): In function `vsv_DeleteConn':
vsv.c.text+0x3b0): undefined reference to `pmap_unset'
/home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a(mesg.o): In function `vsv_Write1Arg':
mesg.c.text+0x1041): undefined reference to `xdr_u_char'
mesg.c.text+0x105e): undefined reference to `xdr_u_char'
mesg.c:(.text+0x109e): undefined reference to `xdr_int'
mesg.c:(.text+0x10cb): undefined reference to `xdr_int'
mesg.c:(.text+0x10f8): undefined reference to `xdr_u_int'
mesg.c:(.text+0x1137): undefined reference to `xdr_int'
mesg.c:(.text+0x1160): undefined reference to `xdr_int'
mesg.c:(.text+0x1170): undefined reference to `xdr_int'
mesg.c:(.text+0x11b1): undefined reference to `xdr_u_int'
mesg.c:(.text+0x11c4): undefined reference to `xdr_opaque'
/home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a(mesg.o): In function `vsv_WriteArgs':
mesg.c:(.text+0x1259): undefined reference to `xdr_u_int'
/home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a(mesg.o): In function `vsv_WriteMesg':
mesg.c:(.text+0x1322): undefined reference to `xdr_u_char'
mesg.c:(.text+0x1360): undefined reference to `xdr_u_int'
mesg.c:(.text+0x1374): undefined reference to `xdr_opaque'
mesg.c:(.text+0x1384): undefined reference to `xdr_u_int'
mesg.c:(.text+0x13c5): undefined reference to `xdrrec_endofrecord'
/home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a(mesg.o): In function `vsv_ReadArgs':
mesg.c:(.text+0x14d8): undefined reference to `xdr_u_int'
mesg.c:(.text+0x15c2): undefined reference to `xdr_u_char'
mesg.c:(.text+0x15df): undefined reference to `xdr_u_char'
mesg.c:(.text+0x164f): undefined reference to `xdr_int'
mesg.c:(.text+0x1660): undefined reference to `xdr_int'
mesg.c:(.text+0x16bc): undefined reference to `xdr_u_int'
mesg.c:(.text+0x16e1): undefined reference to `xdr_int'
mesg.c:(.text+0x173d): undefined reference to `xdr_int'
mesg.c:(.text+0x174e): undefined reference to `xdr_int'
mesg.c:(.text+0x1781): undefined reference to `xdr_u_int'
mesg.c:(.text+0x17b4): undefined reference to `xdr_opaque'
/home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a(mesg.o): In function `vsv_ReadMesg':
mesg.c:(.text+0x184a): undefined reference to `xdrrec_skiprecord'
mesg.c:(.text+0x1860): undefined reference to `xdr_u_char'
mesg.c:(.text+0x1895): undefined reference to `xdr_u_int'
mesg.c:(.text+0x18c2): undefined reference to `xdr_opaque'
mesg.c:(.text+0x18e9): undefined reference to `xdr_u_int'
mesg.c:(.text+0x1931): undefined reference to `xdrrec_eof'
/home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a(mesg.o): In function `vsv_InitSockStat':
mesg.c:(.text+0x1a30): undefined reference to `xdrrec_create'
mesg.c:(.text+0x1a53): undefined reference to `xdrrec_create'
/home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a(sockutil.o): In function `vsv_BindAndListen':
sockutil.c:(.text+0x30e): undefined reference to `pmap_getport'
sockutil.c:(.text+0x33b): undefined reference to `pmap_unset'
sockutil.c:(.text+0x35b): undefined reference to `pmap_set'
/home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a(sockutil.o): In function `vsv_PortChanged':
sockutil.c:(.text+0x3da): undefined reference to `pmap_getport'
/home/edatools/synopsys/vera-2009.12-9/vera_vD-2009.12-9_amd64/lib/vlog/libVeraVcs.a(sockutil.o): In function `vsv_Connect':
sockutil.c:(.text+0x563): undefined reference to `pmap_getport'
sockutil.c:(.text+0x57b): undefined reference to `clnt_spcreateerror'
collect2: ld returned 1 exit status
make: *** [product_timestamp] Error 1
Make exited with status 2
CPU time: 14.619 seconds to compile + .758 seconds to elab + 1.367 seconds to link