TIGFET10nm Open Source Predictive Process Design Kit v1.0

轩辕志瑜 · 发表于 2022-12-6 17:59:32

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本帖最后由轩辕志瑜于 2022-12-6 22:12 编辑

Copyright (c) [2019] [Laboratory for NanoIntegrated Systems]

This repository is a process design kit for Cadence Virtuoso® describing a TIGFET 10nm silicon nanowire device technology. The design kit is derived using Synopsys Sentaurus TCAD® based device simulations.

This kit consists of a SPICE model and full custom physical design files including a Design Rule Manual, a Design Rule Check, and a Layout Versus Schematic decks for Mentor Graphics Calibre®.

TIGFET10nm PDK Directory Structure

calibre/ -> SVRF rules for Mentor Graphics Calibre®
cdslib/ -> Technology libraires for Cadence Virtuoso and setup scripts
hspice/ -> Simulation models for Synopsys HSPICE®
doc/ -> Documentation

For more detail about the key assumptions made while designing this PDK, please refer to the following publication:

Ganesh Gore, Patsy Cadareanu, Edouard Giacomin, and Pierre-Emmanuel Gaillardon "A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors", 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 6-9 October 2019.

Design Kit Installation and Usage (assuming a csh/tcsh shell)
1. Clone the github repository.

git clone https://github.com/LNIS-Projects/TIGFET-10nm-PDK.git
cd TIGFET-10nm-PDK

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2. Set the variable PDK_DIR to where the PDK folder is.

setenv PDK_DIR "$PWD"

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3.Copy the required user files to where you want to start Virtuoso®. It is assumed here that Virtuoso is started in the Github folder itself.

source $PDK_DIR/cdslib/setup/setup.csh

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Note that this script copies all of the required user files (.cdsinit, cds.lib, and Calibre® runset files) to the current working directory if they do not already exist.

4.Source your setup scripts for Cadence Virtuoso®, Mentor Graphics Calibre®, and Synopsys HSPICE® and launch Cadence Virtuoso® using the provided script:

source launch_tigfet10nm.sh

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In case of any doubts/questions/suggestions, please raise issue on GitHub or send an email to pierre-emmanuel.gaillardon@utah.edu or ganesh.gore@utah.edu.

TIGFET-10nm-PDK-ganesh_dev.zip (2.1 MB, 下载次数: 27 )

TIGFET-10nm-PDK-layout-tigfet15nm.zip (3.09 MB, 下载次数: 25 )

TIGFET-10nm-PDK-drc-updates.zip (2.73 MB, 下载次数: 26 )

TIGFET-10nm-PDK-master.zip (2.73 MB, 下载次数: 25 )

TIGFET-10nm-PDK-logic-gates.zip (3.47 MB, 下载次数: 26 )

定版号版本，与前面的相比多了calibre用的检查规则文件。下载完删除最后的那个.gz后缀命

TIGFET-10nm-PDK-v1.0.zip.gz.013.gz (17.12 MB, 下载次数: 22 )

TIGFET-10nm-PDK-v1.0.zip.gz.012.gz (30 MB, 下载次数: 24 )

TIGFET-10nm-PDK-v1.0.zip.gz.010.gz (30 MB, 下载次数: 23 )

TIGFET-10nm-PDK-v1.0.zip.gz.009.gz (30 MB, 下载次数: 23 )

TIGFET-10nm-PDK-v1.0.zip.gz.011.gz (30 MB, 下载次数: 28 )

TIGFET-10nm-PDK-v1.0.zip.gz.008.gz (30 MB, 下载次数: 23 )

TIGFET-10nm-PDK-v1.0.zip.gz.007.gz (30 MB, 下载次数: 25 )

TIGFET-10nm-PDK-v1.0.zip.gz.006.gz (30 MB, 下载次数: 21 )

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TIGFET-10nm-PDK-v1.0.zip.gz.002.gz (30 MB, 下载次数: 25 )

TIGFET-10nm-PDK-v1.0.zip.gz.001.gz (30 MB, 下载次数: 24 )

icroad · 发表于 2022-12-6 20:31:34

多谢分享

hamandu · 发表于 2022-12-6 20:57:52

谢谢分享

lhyi · 发表于 2022-12-7 16:58:16

谢谢分享!!

gubels · 发表于 2022-12-16 10:06:11

Tx for sharing , learning is good..

frains · 发表于 2023-4-17 15:25:54

感谢分享

cmmjava · 发表于 2024-3-17 20:38:06

感谢分享

cmmjava · 发表于 2024-3-31 01:45:40

感谢分享

cmmjava · 发表于 2024-3-31 01:50:48

感谢分享

cmmjava · 发表于 2024-3-31 01:51:38

感谢分享

[资料] TIGFET10nm Open Source Predictive Process Design Kit v1.0

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