弗吉尼亚理工大学硕博士论文

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Digital Control For Power Factor Correction

ABSTRACT
This thesis focuses on the study, implementation and improvement of a digital
controller for a power factor correction (PFC) converter.
The development of the telecommunications industry and the Internet demands
reliable, cost-effective and intelligent power. Nowadays, the telecommunication
power systems have output current of up to several kiloamperes, consisting of
tens of modules. The high-end server system, which holds over 100 CPUs,
consumes tens of kilowatts of power. For mission-critical applications,
communication between modules and system controllers is critical for reliability.
Information about temperature, current, and the total harmonic distortion (THD)
of each module will enable the availability of functions such as dynamic
temperature control, fault diagnosis and removal, and adaptive control, and will
enhance functions such as current sharing and fault protection. The dominance
of analog control at the modular level limits system-module communications.
Digital control is well recognized for its communication ability. Digital control will
provide the solution to system-module communication for the DC power supply.
The PFC converter is an important stage for the distributed power system (DPS).
Its controller is among the most complex with its three-loop structure and
multiplier/divider. This thesis studies the design method, implementation and cost
effectiveness of digital control for both a PFC converter and for an advanced
PFC converter. Also discussed is the influence of digital delay on PFC
performance. A cost-effective solution that achieves good performance is
provided. The effectiveness of the solution is verified by simulation.
The three level PFC with range switch is well recognized for its high efficiency.
The range switch changes the circuit topology according to the input voltage
level. Research literature has discussed the optimal control for both rangeswitch-
off and range-switch-on topologies. Realizing optimal analog control
requires a complex structure. Until now optimal control for the three-level PFC
with analog control has not been achieved. Another disadvantage of the threelevel
PFC is the output capacitor voltage imbalance. This thesis proposes an
active balancing solution to solve this problem.

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Advanced Semiconductor Device and Topology for High Power Current Source Converter

ABSTRACT
This dissertation presents the analysis and development of an innovative semiconductor
device and topology for the high power current source converter (CSC).
The CSC is very attractive in high power applications due to its lower output dv/dt, easy
regeneration capability and implicit short-circuit protection. Traditionally, either a symmetrical
gate turn-off (GTO) thyritor or an asymmetrical GTO in series with a diode is used as the power
switch in the CSC. Since the GTO has a lower switching speed and requires a complicated gate
driver, the symmetrical GTO based CSC usually has low dynamic response speed and low
efficiency. To achieve high power rating, fast dynamic response speed and low harmonics, an
advanced semiconductor device and topology are needed for the CSC.
Based on symmetrical GTO and power MOSFET technologies, a symmetrical emitter turn-off
(ETO) thyristor is developed that shows superior switching performance, high power rating and
reverse voltage blocking capability. The on-state characteristics, forced turn-on characteristics,
forced turn-off characteristics and the load-commutated characteristics are studied. Test results
show that although the load-commutation loss is high, the developed symmetrical ETO is
suitable for use in high power CSC due to its low conduction loss, fast switching speed and
reverse voltage blocking capability.
The snubberless turn-on capability is preferred for a semiconductor device in a power
conversion system, and can be achieved for devices with forward biased safe operation area
(FBSOA). The FBSOA of the ETO is investigated and experimentally demonstrated. The ETO
device has excellent FBSOA due to the negative feedback provided by the emitter switch.
However, the FBSOA for a large area ETO is poor. A new ETO concept is therefore proposed
for future development in order to demonstrate the FBSOA over a large area device.
To improve the turn-on performance of the large area ETO, a novel concept, named the
transistor-mode turn-on, is proposed and studied. During the transistor-mode turn-on process, the
ETO behaves like a transistor instead of a thyristor. Without a snubber, the transistor-mode turnon
for the ETO is hard to achieve. Through the selection of a proper gate drive and di/dt snubber,
the transistor-mode turn-on can be implemented, and the turn-on performance for the ETO can
be dramatically improved.
To increase the power rating of the CSC without degrading the utilization of power
semiconductor devices, a novel multilevel CSC, named the parallel-cell multilevel CSC, is
proposed. Based on a six-switch CSC cell, the parallel-cell multilevel CSC has the advantages of
high power rating, low harmonics, fast dynamic response and modularity. Therefore, it is very
suitable for high power applications. The power stage design, modeling, control and switching
modulation scheme for a parallel-cell multilevel CSC based static var compensator (STATCOM)
are analyzed and verified through simulation.

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High-Frequency and High-Performance VRM Design for the Next Generations of Processors

(ABSTRACT)
It is perceived that Moore’s Law will prevail at least for the next decade with the
continuous advancement of processing technologies for integrated circuits. According to Intel’s
roadmap, over one billion transistors will be integrated in one processor by the year 2010; the
processor’s clock speed will approach 15 GHz; the core static currents will increase up to 200 A;
the dynamic current slew rate will rise up to 250 A/ns; and the core voltage will decrease to 0.8
V. The rapid advancement of processor technology has posed stringent challenges to power
management for both an efficient power delivery and an accurate voltage regulation.
The primary objectives of this dissertation are to understand the fundamental limitations of
the state-of-the-art solution for the power management, and hence to support possible solutions
for meeting the power requirement of the next generations of processors.
First, today’s voltage-regulator module (VRM) design, which is based on the multiphase
interleaving buck topology, is thoroughly analyzed. The analysis results of the control
bandwidths versus the VRM transient voltage spikes highlight the trend of high-frequency VRM
design for smaller size and faster transient response. Based on the concept of achieving constant
VRM output impedance, design guidelines are proposed for different kinds of control methods.
However, the high switching-related losses in the conventional multiphase buck converter limit
its further applications. This dissertation proposes a series of new topologies in order to break
through the barriers by applying an inductor-coupling or autotransformer structure to reduce the
switching-related losses by extending the duty cycle. Then, this dissertation pushes the topology
innovation further by introducing soft-switching quasi-resonant converters for the VRM design.
The combination of the quasi-resonant and active-clamped concepts derives a family of new
converters, which can eliminate all the switching and body-diode losses. The experimental
results at 1-2MHz switching frequencies prove that the proposed solutions for the VRM design
can realize very high efficiency and high power density.

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Modeling and Characterization of a PFC Converter in the Medium and High Frequency Ranges for Predicting the Conducted EMI

Abstract
This thesis presents the conducted electro-magnetic interference (EMI) prediction results
for a continuous conduction mode (CCM) power factor correction (PFC) converter as
well as the theoretical analysis for the noise generation and propagation mechanisms.
In this thesis, multiple modeling and characterization techniques in the medium and high
frequency ranges are developed for the circuit components that are important contributors
to the EMI noise, so that a detailed simulation circuit for EMI prediction can be
constructed.
The conducted EMI noise prediction from the simulation circuit closely matches the
measurement results obtained by a spectrum analyzer. Simulation time step and noise
separator selection are two important issues for the noise simulation and measurement.
These two issues are addressed and the solutions are proposed.
The conducted EMI generation and propagation mechanisms are analyzed in a systematic
way. Two loop models are proposed to explain the EMI noise behavior. The effects of the
PFC inductor, the parasitic capacitance between the device and the heatsink, the
rising/falling time of the MOSFET VDS voltage, and the input wires are studied to verify
the validity of the loop models.

[ 本帖最后由 megafit 于 2008-1-11 11:12 编辑 ]

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Integrated EMI/Thermal Design for Switching Power Supplies

ABSTRACT
This work presents the modeling and analysis of EMI and thermal performance
for switch power supply by using the CAD tools. The methodology and design guidelines
are developed.
By using a boost PFC circuit as an example, an equivalent circuit model is built
for EMI noise prediction and analysis. The parasitic elements of circuit layout and
components are extracted analytically or by using CAD tools. Based on the model, circuit
layout and magnetic component design are modified to minimize circuit EMI. EMI filter
can be designed at an early stage without prototype implementation.
In the second part, thermal analyses are conducted for the circuit by using the
software Flotherm, which includes the mechanism of conduction, convection and
radiation. Thermal models are built for the components. Thermal performance of the
circuit and the temperature profile of components are predicted. Improved thermal
management and winding arrangement are investigated to reduce temperature.
In the third part, several circuit layouts and inductor design examples are checked
from both the EMI and thermal point of view. Insightful information is obtained.

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Low-voltage High-efficiency Fast-transient Voltage Regulator Module

ABSTRACT
In order to meet demands for faster and more efficient data processing, modern
microprocessors are being designed with lower voltage implementations. The processor
voltage supply in future generation processors will decrease to 1.1 V ~ 1.8V. More
devices will be packed on a single processor chip, and processors will operate at higher
frequencies, beyond 1GHz. Therefore, microprocessors need aggressive power
management. Future generation processors will draw current up to 50 A ~ 100 A [2].
These demands, in turn, will require special power supplies and Voltage Regulator
Modules (VRMs) to provide lower voltages with higher currents and fast transient
capabilities for microprocessors.
This work presents several low-voltage high-current VRM technologies for future
generation data processing, communication, and portable applications. The developed
advanced VRMs with these new technologies have advantages over conventional ones in
power density, efficiency, transient response, reliability, and cost.
The multi-module interleaved quasi-square-wave VRM topology achieves a very
fast transient response and a very high power density. This topology significantly reduces
the filter inductance and capacitance, while having small output and input ripples. The
analysis, design, and experimental verification for this new topology are presented in this
work.
The current sensing and current sharing techniques are developed with simple and
cost-effective implementations. With this technique, traditional current transformers and
sensing resistors are not required, and the inductance value, MOSFET on resistance and
other parasitics have no effect on current sharing results. The design principles are
developed and experimentally verified. A generalized approach and an extension of the
novel current sharing control are presented in this work.
The techniques for improving VRM light load efficiency are developed in this
work. By utilizing the duty cycle signal, VRMs can be implemented with advanced
power management functions to reduce further the power consumption at light loads to
extend the battery-operation time in portable systems or to facilitate the compliance with
various "energy star" ("green" power) requirements in office systems. Four improved
approaches are presented and verified with experimental results.
The high-input-voltage VRM topology, push-pull forward converter, can be used
in high-bus-voltage distributed power systems. This converter has a high efficiency, a
high power density, a fast transient response, and can be easily packaged as a standard
module. The circuit design and experimental evaluation are addressed to demonstrate the
operation principles and advantages of this topology.

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IMPLEMENTATION OF A NOVEL SOFT-SWITCHING INVERTER FOR SWITCHED RELUCTANCE MOTOR DRIVES

ABSTRACT
The purpose of this thesis is to design, develop, implement and test a novel soft-switching
inverter topology suitable for switched reluctance motor drives. Present research being
done in the field of switched reluctance motor drive inverters, including soft-switching
inverters, is discussed. The novel topology is presented and the principle of operation is
described in detail. The validity of the topology is verified through simulation. The
various components of the system are designed and the hardware implementation is
presented. Experiments carried out to verify the operation of this inverter are explained.
Results are presented and comparison is made between hard switching and soft switching
inverter topologies. Conclusions are drawn regarding the effectiveness of the proposed
topology.

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A High Performance DSP Based System Architecture for Motor Drive Control

Abstract
This paper presents a high speed digital signal processor (DSP) based
system architecture for motor drive control. The system achieves fast speed
performance by using the 50 MHz TMS320C25 DSP and specialized digital
hardware to perform data acquisition and output control tasks usually
performed in software. The peripheral hardware has been designed for easy
interface to many types of motor drive systems, to make the system generally
applicable in the motion control field. The specifications, systematic design,
and realization of this general purpose controller are described. Software to
support the features of the system is discussed. Experimental results using
the proposed system to control a switched reluctance motor drive, both in
torque mode and four quadrant speed operation, verify the speed
performance of the DSP based system.