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#在这里快速回复# 本帖最后由 2046 于 2022-11-8 13:22 编辑 This book focuses on the use of algorithmic high-level synthesis (HLS) to build application-specific FPGA systems. Our goal is to give the reader an appreciation of the process of creating an optimized hardware design using HLS. Although the details are, of necessity, different from parallel programming for multicore processors or GPUs, many of the fundamental concepts are similar. For example, designers must understand memory hierarchy and bandwidth, spatial and temporal locality of reference, parallelism, and tradeoffs between computation and storage. This book is a practical guide for anyone interested in building FPGA systems. In a university environment, it is appropriate for advanced undergraduate and graduate courses. At the same time, it is also useful for practicing system designers and embedded programmers. The book assumes the reader has a working knowledge of C/C++ and includes a significant amount of sample code. In addition, we assume familiarity with basic computer architecture concepts (pipelining, speedup, Amdahl’s Law, etc.). A knowledge of the RTL-based FPGA design flow is helpful, although not required. The book includes several features that make it particularly valuable in a classroom envi- ronment. It includes questions within each chapter that will challenge the reader to solidify their understanding of the material. There are associated projects that were developed and used in the HLS class taught at UCSD (CSE 237C). We will make the files for these projects available to instructors upon request. These projects teach concepts in HLS using examples in the domain of digital signal processing with a focus on developing wireless communication systems. Each project is more or less associated with one chapter in the book. The projects have reference designs targeting FPGA boards distributed through the Xilinx University Program (http://www.xilinx.com/support/university.html). The FPGA boards are available for com- mercial purchase. Any reader of the book is encouraged to request an evaluation license of Vivadoà HLS at http://www.xilinx.com. iShot_2022-11-01_00.07.26.png Parallel Programming for FPGAs |
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发表于 2022-11-6 00:12:07
