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PhaseLockedLoop_2006--DESIGN

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发表于 2008-1-10 21:18:52 | 显示全部楼层 |阅读模式

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PhaseLockedLoop_2006--DESIGN

PhaseLockedLoop_2006--DESIGN.pdf

1.19 MB, 下载次数: 280 , 下载积分: 资产 -2 信元, 下载支出 2 信元

发表于 2008-1-10 22:10:31 | 显示全部楼层
看看!!!
发表于 2008-1-11 01:15:23 | 显示全部楼层
看看看看看
发表于 2008-1-11 01:16:16 | 显示全部楼层
貌似不错啊
发表于 2008-1-11 08:26:26 | 显示全部楼层
发表于 2008-1-11 08:33:16 | 显示全部楼层
发表于 2008-1-11 08:39:21 | 显示全部楼层
thanks
发表于 2008-1-11 08:40:51 | 显示全部楼层
Table Of Contents
Abstract .......................................................................................................................................... 1
Acknowledgments.......................................................................................................................... 2
1. Introduction................................................................................................................................ 4
1.1 Motivation............................................................................................................................ 4
1.2 Application: Clock Generator and Frequency synthesizer ................................................... 4
2. Phase Locked Loop System Fundamentals................................................................................. 5
2.1 System Overview.................................................................................................................. 5
2.2 Phase Detector ...................................................................................................................... 6
2.3 Charge Pump / Low Pass Filter .......................................................................................... 13
2.4 Voltage Controlled Oscillator ............................................................................................. 22
2.4.1 VCO Architectures ....................................................................................................... 22
2.4.2 VCO Design: Delay Cell.............................................................................................. 23
2.4.3 VCO Design: Replica Bias........................................................................................... 24
2.4.4 VCO Design: Transistor Sizing ................................................................................... 26
2.4.5 VCO Design: Differential to Single-Ended Converter ................................................ 26
2.4.6 VCO Design: Characteristic Plot ................................................................................ 28
2.5 Low Pass Filter and Transfer Function............................................................................... 29
2.5.1 Specifications of the PLL Design................................................................................. 32
2.6 Final Simulation Results ..................................................................................................... 33
2.6.1 Final PLL Schematic.................................................................................................... 33
2.6.2 PLL Simulations in Unlock State ................................................................................. 34
2.6.3 PLL Simulations in Locked State ................................................................................. 38
2.7 VCO Layout........................................................................................................................ 40
2.8 Future Improvements .......................................................................................................... 43
2.8.1 Power Reduction.......................................................................................................... 43
2.8.2Minimize Glitches in the Output ................................................................................... 44
2.8.3 Increase Bandwidth ..................................................................................................... 44
3. Societal Issues.......................................................................................................................... 44
3.1 Engineering Standards and Constraints .............................................................................. 44
3.1.1 Economic...................................................................................................................... 44
3.1.2 Sustainability................................................................................................................ 45
3.1.3Manufacturability ......................................................................................................... 45
3.1.4 Environmental.............................................................................................................. 45
3.1.5 Social........................................................................................................................... 45
3.2 Cost Analysis ...................................................................................................................... 45
4. Conclusion ............................................................................................................................... 46
Works Cited ................................................................................................................................. 48
发表于 2008-1-11 15:43:30 | 显示全部楼层

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发表于 2008-1-11 17:53:30 | 显示全部楼层
good good
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