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This paper presents an area-efficient split capacitive array architecture for high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs). The equivalent value method is proposed to adjust the bridge capacitance as an integer value so that the bridge capacitance can match well with the unit capacitance. A split capacitive array with redundancy is utilized in a 16-bit SAR ADC and the total required number of the unit capacitors is only 452. Four proposed static pre-amplifiers enhance the noise performance and the offset performance of the comparator and a proposed dynamic latch enhances the speed performance. As a result, the 180 nm design can achieve a 1 MS/s sampling rate with a single channel. The spurious-free dynamic range is 105.85 dB while the effective number of bits can reach 15.78 bits with a Nyquist-rate input while consuming 32 mW from a 5 V supply. The resultant Schreier and Walden figures of merit are 168 dB and 457 fJ/conversion-step respectively. The proposed SAR ADC occupies an active area of 4200 \(\upmu \mathrm{m}\) by 2200 \(\upmu \mathrm{m}\).
谁帮忙下载一下这篇文章呢?好像是成都华威电子公司做的,指标非常好啊,想学习学习。
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