Responsibilities: The candidate is expected to be responsiblefor following tasks 1. Participate in SOC full chip DFT featureand architecture definition 2. Implement SOC DFT function includingSCAN, Boundary SCAN, MBIST, Analog Macro test logic. 3. Generate DFT related timing constraintsand work for timing closure 4. Develop and verify high coverage andcost-effective test patterns for the production test 5.Evaluate and establish the advanced DFTtools and flow Qualifications: 1. 8+ years’ experience for Bachelor or 3+ years for Master in DFTdesign and verification, test pattern development 2. Good Knowledge of Scan/ATPG, MBIST andboundary scan and other DFT techniques 3. Good Knowledge of industry DFT toolslike DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc. 4. Good knowledge of digital SoC/ASICdesign, including STA, verification and RTL coding 5. Proficient in hardware descriptionlanguages such as Verilog, System Verilog and VHDL 6. Good Knowledge of script language, suchas Tcl, Python, Perl 7. Good English communication skills 8. Strong commitment to schedule and workquality, good team player
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