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Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme
Abstract—This paper presents a basic two-stage CMOS opamp
design procedure that provides the circuit designer with a means
to strike a balance between two important characteristics in
electronic circuit design, namely noise performance and power
consumption. It is shown in this paper that, unlike the previously
reported design procedures, the proposed design step allows
opamp designers to trade between noise performance and power
consumption with greater flexibility. In order to verify the viability
of the proposed design step, SPICE simulation results of the
opamp designed by the proposed procedure, under a variety of
temperature and process conditions, are given.
Index Terms—CMOS analog integrated circuits, frequency compensation,
operational amplifier, poles and zeroes. |
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