DFT资料:Design for Test Standrad by J. M. Martins Ferreira

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前言与前两章目录

Foreword
This version V1.1 of the Design for Test Standards text belongs to the set of
deliverables under the responsibility of FEUP and is intended to guide an
applications-oriented approach to the area of testable circuits design. It is
important to emphasise the applications-oriented approach underlying the
development of this course material, essentially intended to be used in a laboratory
environment, more than in a classroom environment.
Two types of additional resources are required to support the hands-on sessions:
• A hardware complement to this text, in the form of a demonstration board that
illustrates in practice the problems and possible solutions related to testing
circuits with boundary scan.
• A Windows application that enables the students to write and execute their
own test programs.
The necessary information for manufacturing demonstration boards is attached as
an annex at the end of chapter 5 (A case study of test program execution) and a set
up diskette for the Windows boundary scan test controller application is included
at the end of this document.
While the general principles of scan-based design for testability are de facto
standards coming from the late 70s, the approval in 1990 of the IEEE 1149.1
boundary scan architecture and test access port greatly improved industry
acceptance and made scan design techniques accessible to any designer. This trend
was consolidated in June of 1999, with the approval of the IEEE 1149.4 standard
for mixed-signal testing, which explains why these two standards form the basis of
the present text.


TABLE OF CONTENTS
ACRONYMS
GLOSSARY
1. BASIC TEST CONCEPTS
1.1 Fault modeling and ss@ faults ............................................................ 1.1
1.2 Controllability, observability and testability ..................................... 1.2
1.3 Test vector generation for combinational circuits.............................. 1.4
1.4 Testability and test generation in sequential circuits ....................... 1.7
1.5 Testability improvement via ad hoc solutions.................................. 1.11
1.6 Structured approaches to design for testability ............................... 1.12
1.7 Hands-on............................................................................................ 1.20
2. THE BOUNDARY SCAN TEST (BST) TECHNOLOGY
2.1 The development of BST and its application domain ........................ 2.1
2.2 The BS architecture and test access port (TAP) ................................ 2.2
2.2.1 The basic boundary scan cell....................................................................2.5
2.2.2 The test data registers..............................................................................2.6
2.2.3 The instruction register............................................................................2.7
2.2.4 The TAP controller ...................................................................................2.8
2.3 Implementation of an 1149.1 BST architecture on a MACH
programmable logic device ................................................................ 2.10
2.4 Hands-on............................................................................................ 2.19
2.4.1 BST infrastructure validation................................................................2.19
2.4.2 BST infrastructure expansion for fault tolerance validation ................ 2.20
2.4.3 BST infrastructure expansion for real-time breakpoint detection........ 2.21

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