请问怎么用liberty文件生成verilog文件？

starrace

似乎老版本library compiler可以用下面这个命令生成verilog
'write_lib -format verilog'
但2018版会报错说format只能选db
请问各位大佬verilog文件要怎么生成呢？想ptpx用

Lotusy

如果你是缺db的话，lib可以生成db，用lc_shell  read_lib .lib  write_lib name -f db -o .db

starrace

Lotusy 发表于 2022-4-28 14:39
如果你是缺db的话，lib可以生成db，用lc_shell  read_lib .lib  write_lib name -f db -o .db ...

db是有的，但是想生成verilog库。

Lotusy

ncx：
Generating Verilog Files
Library Compiler generates a Verilog model from a .lib file and creates a cell.v Verilog file for each cell in the library. By default, Library Compiler creates the cell.v files in the user-defined library_name_verilog directory, under the current working directory. If the library_name_verilog directory already exists under the current working directory, the newly generated cell.v files overwrite the existing files in the directory, and Library Compiler issues a warning message.
Use the following commands to generate Verilog models:
1.To enable Verilog model generation, set the veriloglib_enable variable to true. By default, the variable is set to false, and a Verilog file is not generated.
set veriloglib_enable [true | false]
2.To create a Verilog file from a .lib file, run the write_lib command in lc_shell and specify the .lib library name as shown:
write_lib -format verilog library_name

starrace

Lotusy 发表于 2022-4-29 15:10
ncx：
Generating Verilog Files
Library Compiler generates a Verilog model from a .lib file and creat ...

多谢回复，但我用的lc2018版本这样操作会报错