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求教 再synplify dc中出现这个问题怎么解决
Implementation : rev_3
Synopsys Xilinx Technology Pre-mapping, Version map202009syn, Build 093R, Built Nov 25 2020 14:41:12, @1021986
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 229MB peak: 229MB)
@W:BN289 : | View view:work.DW_minmax_4s_8s_3s_18446744073709551608s(verilog) requires license DesignWare: treating view as black box
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