MIPS Verilog文献中一句话不太理解

come_on_sn

      

The Verilog model for the processor is organized as shown in Figure 9-5. The instruction memory, data memory, and register file are created as components with
their architecture and entity descriptions.
句1：处理器的Verilog模型如上图所示。指令存储器、数据存储器、寄存器文件分别被创建为具有构造体和实体描述的模块。


The main code, the MIPS entity, embeds the control sequencing the instructions through the various stages of its operation.
句2：顶层文件MIPS实体嵌入了通过其操作的各个阶段对指令进行排序的控制。


【求助】因为我第一次接触MIPS，理解不是很到位，有没有大神知道句2应该怎么翻译，会比较贴切易懂呢？感恩！