CICC2007 Pipeline ADC

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根本不全嘛,还有这篇没有.
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process
Singh, P.N.  Kumar, A.  Debnath, C.  Malik, R.  
STMicroelectron., Noida  

This paper appears in: Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Issue Date: 16-19 Sept. 2007
On page(s): 189 - 192
Location: San Jose, CA
Print ISBN: 978-1-4244-1623-3
Cited by: 2
INSPEC Accession Number: 9803938
Digital Object Identifier: 10.1109/CICC.2007.4405710
Date of Current Version: 21 一月 2008
Abstract
This paper describes a novel low power 10-bit 125 Msps pipelined ADC implemented in 65 nm standard digital CMOS process. Proposed ADC implements 2.5 b/stage with amplifier shared between consecutive stages, achieves best in class FOM of 0.27 pJ/step with conversion power of 0.16 mW/Msps. The ADC amplifier employs novel techniques of adaptive biasing and cross coupled compensation to achieve improved settling behavior with significant power efficiency. This ADC occupies 0.13mm area and achieves maximum 0.3 LSB DNL and 0.6 LSB INL along with 9.26 ENOB at 125 Msps dissipating 20 mW power from 1.2v supply.