招Asic设计工程师，大厂高薪

ritaguo123

Job Responsibilities:

Responsible for integrating IP modules and designing glue logic at chip’s top level. Responsibilities include:

·Contributing to the investigation and definition of a device feature set and requirements

·Participating in micro-architecture documentation

·Integrating IP modules, designing glue logic, interfacing with verification and emulation groups

·Performing development activities such as Synthesis, Formal Verification, Clock Domain Crossing (CDC) analysis, and Static Timing Analysis

·Assisting implementation group on backend flowQualifications:

·2+ years of experience

·Proficient in Verilog/System Verilog

·Experience with integrating IP modules, and designing glue logic at the top level

·Worked with Implementation team in ASIC backend flow

·Experience with ARM processors, CMN Coherent Interconnect, Coresight, SMMU, GIC, PCIe and DDR is an asset

·Synthesis, Static Timing Analysis, and Logical Equivalency checking experience is an asset

·Excellent analytical and debugging skills

企业优势：
专注于云计算和数据中心数据处理器芯片和解决方案的领先初创公司，由原RMI公司(后被Netlogic/Broadcom并购)co-founder Sunny Siu博士联合业界精英联合创立，核心团队来自Broadcom、Intel、阿里巴巴、海思和Arm等，拥有中国最有经验的DPU芯片设计和软件研发团队
薪资构成：
现金+期权，60w以上16薪，60w以下14薪
联系方式： Mobile:18617135109  QQ：3434957652        WeChat：13310878819