【虚拟机】Ubuntu20.04下集成 Cadence IC618，Spectre21，Calibre20，XCELIUMMAIN_18

dragonyanhao

silverstar66 发表于 2023-3-22 14:28
知乎搜 “我是青藤” 用户。他的EDA仿真环境文章里有分享。如果不是必须要用Ubuntu ，可以下载他的centos ...

谢谢啊，已经关注了。

sinsic

太辛苦了，应该加鸡腿

yejingang

赶紧支持

pinkoman

要怎么在这个虚拟机里自己安装hspice&wv呢

yyhan

XCELIUMMAIN_18 为啥跑单独数字仿真不行，混合仿真可以？  csi-xmsim - CSI: *F,INTERR: INTERNAL EXCEPTION,有人遇到这个问题吗？
错误如下：

                Always blocks:                 4       4
                Initial blocks:              295     155
                Clocking blocks:               2       2
                Clocking items:               10      10
                Parallel blocks:              29      30
                Pseudo assignments:            7       7
                Assertions:                    3       3
                SV Class declarations:       207     315
                SV Class specializations:    399     399
        Writing initial simulation snapshot: worklib.top:sv
Loading snapshot worklib.top:sv .................... Done
SVSEED set from command line: 100
xmsim: *W,RNDNOXCEL: The legacy SystemVerilog constraint solver is used. Enabling the Xceligen constraint solver with "xrun/xmsim -xceligen on ..." is recommended.
xmsim: *F,INTERR: INTERNAL EXCEPTION
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL:        xmsim(64)        18.03-s001
  HOSTNAME: icdesign-Ubuntu
  OPERATING SYSTEM: Linux 5.15.0-47-generic #51-Ubuntu SMP Thu Aug 11 07:51:15 UTC 2022 x86_64
  MESSAGE: sv_seghandler - trapno -1 addr((nil))
-----------------------------------------------------------------
xmsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
csi-xmsim - CSI: Cadence Support Investigation, sending details to /home/icdesign/IC/Simple_UVM/tb/xmsim_110398.err
csi-xmsim - CSI: investigation complete, send /home/icdesign/IC/Simple_UVM/tb/xmsim_110398.err to Cadence Support
xcelium> source /opt/cadence/XCELIUM1803/tools/xcelium/files/xmsimrc
xcelium> source /opt/cadence/XCELIUM1803/tools/methodology/UVM/CDNS-1.1d/additions/sv/files/tcl/uvm_sim.tcl
xcelium> database -open waves -shm

coverage setup:
  workdir  :  ./cov_work
  dutinst  :  top(top)
  scope    :  scope
  testname :  simple_test-100

coverage files:
  model(design data) :  ./cov_work/scope/icc_10edcd40_00000000.ucm
  data               :  ./cov_work/scope/simple_test-100/icc_10edcd40_00000000.ucd
Created SHM database waves
xcelium> probe -create top -depth all -all -memories -shm -database waves
Created probe 1
xcelium> run
xmsim: *E,RNUNES: End of simulation callbacks already executed, cannot continue.
xcelium> exit
make: *** [Makefile:24: compile] Error 1

tony155

感谢无私分享！

八咫之鸟

请问有人在Ubuntu遇到过Cadence help文件打不开或者空白页面的情况吗，暂时没有什么头绪

generalradec

谢谢楼主，楼主辛苦了！！请问这个是直接下载就能用的吗？我已经搞了一两天了，感觉快崩了。

zhaoqy

请问最新的那个虚拟机里面是有virtuoso的是吧  也是乌班图系统吗

nannan666

多谢您的分享，请问您师弟的那个虚拟机的root密码可以说一下么，谢谢