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楼主 |
发表于 2021-12-22 17:32:57
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Adder:
module adder( so, co,a, b, ci );
input a, b, ci;
output so, co;
wire a, b, c, co,so;
assign {co, so} = a + b + ci;
endmodule
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Adder的testbench:
`timescale 1ns/1ns
module adder_tb;
wire so,co;
reg a,b,ci;
adder U(.so(so),.co(co),.a(a),.b(b),.ci(ci));
initial // initializes the register variable to a definite value of one
begin
#20 a=0;b=0;ci=0;
#20 a=0;b=0;ci=1;
#20 a=0;b=1;ci=0;
#20 a=0;b=1;ci=1;
#20 a=1;b=0;ci=0;
#20 a=1;b=0;ci=1;
#20 a=1;b=1;ci=0;
#20 a=1;b=1;ci=1;
#20 $stop;
end
endmodule |
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