|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current RangePublisher: IEEE
Cite This
[url=][size=1.15]PDF[/url]
[size=0.87][size=0.87]Darshil Patel
[url=]All Authors[/url]
[size=1.2em]114
Full
Text Views
- [size=1.25]
- [size=1.2]
- [url=][size=1.25][/url]
- [url=][size=1.25][/url]
- [url=][size=1.25][/url]
[size=1em]Document Sections
- [size=0.9em][url=]I.
Introduction
[/url] [size=0.9em][url=]II.
Design of High Slew Rate Op-Amp
[/url][size=0.9em][url=]III.
Complete Ldo Regulator Design and its Analysis
[/url][size=0.9em][url=]IV.
Conclusion
[/url]
Abstract ow noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22μs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.
Published in: 2021 4th Biennial International Conference on Nascent Technologies in Engineering (ICNTE)
Date of Conference: 15-16 Jan. 2021
Date Added to IEEE Xplore: 30 July 2021
ISBN Information:
INSPEC Accession Number: 20995393
DOI: 10.1109/ICNTE51185.2021.9487577
Publisher: IEEE
|
|