在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 1663|回复: 8

[转贴] EE290D Lecture Notes Advanced Topics in Semiconductor Technology

[复制链接]
发表于 2021-11-17 09:13:52 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
本帖最后由 andy2000a 于 2021-11-17 09:18 编辑

EE290D Lecture Notes
Advanced Topics in Semiconductor Technology
  - Three-Dimensional Transistor Technologies
  Piazza  and bSpace  sites
Fall 2013

https://inst.eecs.berkeley.edu/~ee290d/fa13/

PDF

https://www-inst.eecs.berkeley.e ... D_LectureNotes.html


(pdf format, unless otherwise noted)


Module I: Device Physics
Lecture 1: course overview, history of multiple-gate MOSFET development marked version
Lecture 2: MOSFET performance metrics, short-channel MOSFET electrostatics, scale length marked version (updated on 9/11)
Lecture 3: advantages of thin-body MOSFETs in electrostatics, Effective drive current marked version

Lecture 4: semiconductor band structure, quantum confinement effect, low-field effective mobility, high-field velocity saturation marked version

Lecture 5: thin-body MOSFETs quantum confinement and carrier mobility, series resistance, apparent mobility, ballistic transport marked version

Lecture 6: MOSFET compact modeling, Technology CAD

Review of Module I


Module II: Device-Process Interactions
Lecture 7: impacts of substrate, bulk vs. SOI FinFETs, Fin patterning, gate stack engineering marked version

                 Introduction to double patterning approaches (Wikipedia)
Lecture 8: FinFET Source/Drain doping, thin-body MOSFET’s threshold voltage engineering marked version
Lecture 9: Strained-Si technology I: device physics: band structure and scattering rates vs. strain marked version

Lecture 10: Strained-Si technology II: process implementation of stressors: eSiGe, SMT, CESL, Gate-Last on Planar and FinFETs

Lecture 11: process-induced performance variability I: Random marked version (updated on 11/5)

Lecture 12: process-induced performance variability II: Systematic marked version


Module III: Device-Circuit Interactions
Lecture 13: digital device’s metrics, energy vs. delay plots, technology advancement on logic circuits
Lecture 14: SRAM technology & designs, scaling trend, FinFET-based SRAM issues, SRAM alternatives
Lecture 15: MPU technology trends, state-of-the-art CMOS platforms: planar MOSFETs and FinFETs

Lecture 16: MOSFET Analog/RF performance metrics, bulk and thin-body MOSFET’s Analog/RF performance
Lecture16.pdf (2.99 MB, 下载次数: 22 )
Lecture 17: back-end-of-line (BEOL) technology, system-level integrations: SiP, TSV and Monolithic 3D

Lecture 18: multiple-floating gate devices, 3-D vertical NAND

其他你們自己抓


 楼主| 发表于 2021-11-17 09:17:52 | 显示全部楼层
Nanoscale CMOS Implications on Analog Mixed-Signal Design

Nanoscale CMOS Implications on Analog Mixed-Signal Design.pdf (2.27 MB, 下载次数: 32 )

发表于 2021-11-17 15:23:55 | 显示全部楼层
goooooooooooooooooooooooood
发表于 2021-11-17 19:46:29 | 显示全部楼层

goooooooooooooooooooooooood
发表于 2021-11-17 21:13:06 | 显示全部楼层
谢谢分享
发表于 2021-11-17 21:20:13 | 显示全部楼层
xxfx谢谢分享
发表于 2022-7-21 23:14:49 | 显示全部楼层
good. thanks for sharing
发表于 2023-7-2 23:34:54 | 显示全部楼层
thanks for sharing
发表于 2023-7-3 10:22:52 | 显示全部楼层
thanks
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /2 下一条

小黑屋| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-6-11 06:01 , Processed in 0.024629 second(s), 7 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表