急招！！北/深/武汉 数字设计工程师 Tel:13310878819

蒋璧闺

联系电话：13310878819  VX:ivy13310878819

工作内容:
作为ASIC IP Design团队的一员，你将会负责以下工作内容（但不限于此）:

- 准备模块级、IP级、芯片级的微架构
- 模块级或子系统级的算法或功能逻辑的RTL实现
- 网表产生和交付，包括Lint、CDC、综合/DCG等等
- 第三方IP的配置、优化，和性能、功能系统集成
- 帮助后端团队进行PR实现和时序分析
- 帮助系统、验证、Bring-up团队做功能和性能的系统测试

技能要求：
- 电子、信息工程、通讯、计算机、自动化，或其他相关专业
- 良好的计算机体系结构知识
- 熟悉Verilog或者SystemVerilog.
- 对ASIC前端设计流程有一定的实际经验或知识
- 自我驱动，自我激励，热爱学习

如有以下一项或者多项是加分项：
- 计算机体系结构知识，比如ARM, RISCV,或MIPS的内核和Cache、TCM.
- FPGA或者IC加速器的实现经验，包括AI/NPU、GPU、ISP、Video、或者通讯系统
- 深度神经网络知识，比如流行的Framework/Network,相关的硬件加速器
- 有大型SOC 系统经验或知识，有完整项目经验
- 有任意以下任务经验：RTL Lint/CDC检查，时序约束产生，综合，形式验证,时序检查
- 熟悉ARM AMBA 总线协议，包括 AXI/AHB/APB, 或者TileLink
- 低功耗实现和经验，包括Clock Gating、多电压域设计和UPF产生


ASIC Design Engineer
Location: Shanghai/Wuhan/Beijing

Job Description:
As a member of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

- Prepare micro-architecture specification for IP, subsystem or chip;
- RTL coding to implement algorithm and functions, module level or sub-system level
- 3rd party IP configuration , optimization, and perform integration into SOCs.
- Netlist generation and PPA optimization, including synthesis/linting/cdc/DCG flow…
- Assist with backend team on perform place-and-route and timing analysis of modules
- Assist with ESL/DV/bring-up team and perform functional/performance validation.

Job Requirements:
- Degree in electrical engineering, computer engineering or related technical fields
- Good knowledge of computer architecture
- Skilled on Verilog and/or SystemVerilog.
- Have knowledge frontend ASIC design methodology/flow.
- A high-level of self-motivation and a proactive approach to solving problems

Solid knowledge in one of the following areas is a plus and will highlight you:
- Knowledge of CPU architecture, either ARM, RISCV, or MIPS，either Core or Cache/TCM
- Knowledge of Deep Learning, popular framework or network, and/or hardware accelerators
- Experience on FPGA or IC hardware implementation, either AI/NPU/GPU/ISP/Video, or communication accelerators.
- Experience on complex SOC projects, take part in full tape out flow
- Experience on any one or more tasks: RTL Lint/CDC check, SDC generation, Synthesis, Formal, STA etc.
- Familiar with AMBA AXI/AHB/APB spec, or Tilelink
- Experience of Low power design， including Multi-PowerDomain design and UPF generation.