数模混合仿真出错

黄焖鸡

ncvlog(64): 14.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: /home/IC/WORK/plib/cds_globals/ts_config/verilog.vams
        module plib.cds_globals:ts_config (up-to-date)
                errors: 0, warnings: 0
ncvlog: Memory Usage - 19.6M program + 22.0M data = 41.6M total
ncvlog: CPU Usage - 0.1s system + 0.0s user = 0.1s total (0.1s, 72.5% cpu)
Successfully compiled ('plib' 'cds_globals' 'ts_config').
ncvlog(64): 14.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: /home/IC/WORK/plib/inv/schematic/verilog.vams
        module plib.inv:schematic (up-to-date)
                errors: 0, warnings: 0
ncvlog: Memory Usage - 19.6M program + 22.1M data = 41.7M total
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 55.2% cpu)
Successfully compiled ('plib' 'inv' 'schematic').
ncvlog(64): 14.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: /home/IC/WORK/plib/d_a/verilogams/verilog.vams
        module plib.d_a:verilogams (up-to-date)
                errors: 0, warnings: 0
ncvlog: Memory Usage - 19.6M program + 22.2M data = 41.8M total
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 100.0% cpu)
Successfully compiled ('plib' 'd_a' 'verilogams').
ncvlog(64): 14.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: /home/IC/WORK/plib/digital/functional/verilog.v
        module plib.digital:functional (up-to-date)
                errors: 0, warnings: 0
ncvlog: Memory Usage - 19.6M program + 22.1M data = 41.8M total
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 100.0% cpu)
Successfully compiled ('plib' 'digital' 'functional').
ncvlog(64): 14.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: /home/IC/WORK/plib/ts/schematic/verilog.vams
        module plib.ts:schematic (up-to-date)
                errors: 0, warnings: 0
ncvlog: Memory Usage - 19.6M program + 22.1M data = 41.7M total
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 61.5% cpu)
Successfully compiled ('plib' 'ts' 'schematic').
Compilation successful.
ncelab(64): 14.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
        Elaborating the design hierarchy:
        ERROR: terminated with error code 127
ncelab: *F,SPRSER: Spice/Spectre file parsing failed.
ncelab: Memory Usage - 46.6M program + 30.0M data = 76.7M total (Peak 76.7M)
ncelab: CPU Usage - 0.2s system + 0.0s user = 0.3s total (0.4s, 58.4% cpu)
Failed to elaborate ("plib" "ts" "config").

编译都没有问题，提示了红色标注的错误，我认为可能是添加model libarary setup那一步出的错。请问怎么解决呢？

黄焖鸡

好像是因为我只有.scs文件没有.lib文件的问题？那这种情况下还怎么仿真呢？