Basic precautions and tips that an Analog Designer should know.
关于模拟集成电路电路设计须知
1. Minimum channel length of the transistor should be four to five times the minimum feature size of the process. We do it, to make the lambda of the transistor low i.e. the rate of change of Id w.r.t to Vds is low.
晶体管最小沟长为工艺最小特征尺寸的4-5倍，用来减小沟长调制效应
2. Present art of analog design still uses the transistor in the saturation region.So one should always keep Vgs of the Transistor 30% above the Vt.
目前模拟集成电路设计仍然是使晶体管工作在饱和区，故应使Vgs大于Vt约30%
3. One should always split the big transistor into small transistors having width or length feature size < or = 15um.
应把大管分成小晶体管，使其宽、长尺寸<或=15um
4. W/L Ratio of transistors of the mirror circuit should be less than or equal to 5, to ensure the proper matching of the transistors in the layout. Otherwise, it results to the Systamatic Offset in the circuit.
电流镜电路的晶体管的w/l比应小于或等于5，以保证较好的Matching,否则会有系统失调
5. One should make all the required pins in the schmetic before generating the layout view. Because it’s diffcult to add a pin in the layout view. All IO pins should be a metal2 pins whereas Vdd and Ground should be metal1 pins
在原理路中画出所有的管脚（pin），之后才作layout。因为在layout中增加一个pin是比较困难的。所有的IO pin应该用metal2 pin，Vdd和GND用metal1 pin
6. One should first simulate the circuit with the typical model parameters of the devices. Since Vt of the trasistor can be anything between Vt(Typical) -/+ 20%. So we check our circuit for the extreme cases i.e. Vt+20%, Vt-20%. A transistor having Vt-20% is called a fast transistor and transistor having Vt+20% is called slow transistor. It’s just a way to differentiate them. So with these fast and slow transistor models we make four combination called nfpf, nfps, nspf, nsps, which are known as process corners. Now, once we are satisfied with the circuit performance with typical models than we check it in different process corners, to take the process variation into account. Vt is just one example of the process variation there are others parameter too.
首先先用tt模型做电路仿真。考虑Vt有+20% (slow)和-20% (fast)的变化,需要对工艺角考虑，FF，SS，FS，SF。除Vt，其他工艺参数也会有变化
7. Its thumb rule that poly resistance has a 20% process variation whereas well resistance has got 10%. But the poly resistance has got lower temperature coefficent and lower Sheet Resistance than well resistance So we choose the resistance type depending upon the requirments. Poly Capacitance has got a process variation of 10%.
多晶硅电阻大约有20%的工艺变化，而阱区电阻变化约为10%。但多晶硅电阻有较低的温度系数和低的方块电阻，应根据需要来选择电阻。多晶硅电容约有10%工艺变化
8. One should also check the circuit performance with the temperature variation. We usuly do it for the range of -40C to 85C.
需考虑温度变化对电路性能的影响，通常在-40C到85C范围
9. One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells.
有覆盖金属层或阱区时，须考虑寄生电容
10. In Layout, all transistors should be placed in one direction, to provide the same environment to all the transistors.
Layout中，所有晶体管统一摆放方向，使有相同的环境
11. One should place all transistor in layout with a due care to the pin position before start routing them.
在对晶体管布局布线之前，考虑Pin的位置
12. One should always use the Metal 1 for horizontal routing and Metal 2 for the vertical routing as far as possible.
尽量使用metal1横向布线，metal2纵向布线
13. One should never use POLY as routing layer when the interconnects carries a current. One can have a short gate connection using poly.
在互连用来传送电流时，不要用Poly来做互连。可以用poly做短的栅连接。
14. One should try to avoid running metal over poly gate. As this cause to increase in parasitic capacitance.
避免金属在多晶硅栅上走线，会增加寄生电容
15. Current in all the transistor and resistor part should flow in the same direction.
所有晶体管和电阻有相同的电流走向
16. One should do the Power(Vdd & Gnd) routing in top layer metal (metal5 only). Because Top layer metals are usually thicker and wider and so has low resistance.
在最上层金属做电源（Vdd和GND）布线。因为最上层金属通常更厚、更宽，因而电阻较小
17. One should always merge drain and source of transistor (of same type) connected together.
merge连接的Source和Drain
18. To minimize the process variation in the Resistor value one should always take the resistor’s width three to four times of the default value. we do it to decrease the value of differential of R(L)
为减小工艺变化对电阻影响，应使电阻的宽度为默认值的3-4倍
19. One should cover the resistance with metal layer, to avoid the damaged during the wafer level testing.
用金属覆盖电阻，避免wafer级测试时的损伤
20. One should always make a Common Centroid structure for the matched transistor in the layout.
* Each differential pair transistor should be divide into four transistors and should be placed in two rows common centroid structure.
* One may use the the linear common centroid structure for the current mirror circuit.
对匹配的晶体管用共中心的结构
*差分对管，分割为4管，2*2排列，共中心
*对电流镜，可用线形共中心
21. It’s advisiable to put a dummy layers around the resistance and the capacitance to avoid the erosion at the time of etching.
建议在电阻和电容周围作dummy
22. One should always have a Guard Ring arround the differential pair.
在差分对周围作保护环
23. Always put a Guard Ring arround the N-well and P-well.
在N阱和P阱作保护环
24. Thumb rule for the metal current density is 0.8mA/um. It’s larger for the top most metal layer.
金属电流密度0.8mA/um，最上层金属可以更大
25. To avoid the Latchup, one should always make the PN junction reverse biased i.e. In NWELL should be connected to positive power supply (Vdd) and PWELL should be connected to negative power supply (Gnd). Designers do it to make the leakage current small.
为避免Latchup，应使PN结反偏，如N-Well应连到正电源，P-Well应连到负电源。这样可减小漏电
26. It’s always a good practice to use a infotext layer to put the name of the device on the top of it in layout and have a netname for every nets in schematic. Designer should put the pin name on the top of the pin with same metaltxt layer because hercuels takes the netname from metaltxt only whereas Diva takes from the pin-name.
在layout中用infotext标明器件名称，在schematic中标明net。用相同的metaltxt层标明pin
27. Cadence SPICE simulator take vdd! & gnd! as a global Vdd and Gnd net i.e. any net ending with ‘ !’ is considered as a global net..
Cadence 仿真工具对以‘!’结尾的net认为全局net
28. Transistor Equation:
Id=(beta/2)*square(Vgs-Vt)
Gm=square root of(2Id*beta)
基本晶体管方程
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发表于 2021-8-16 17:09:59
