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发表于 2021-7-6 12:15:25
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init: 0%
floorplan: small increase due to physical cells such as tap cells, endcap cells
place: small increase due to DRV fixing
CTS: 5-10%. This is very rough estimate. It depends on the design.
route: small increase due to antenna diode insertion, some cell upsizing, maybe some hold fixing buffers
postroute: small increase due to hold fixing.
高宽比太极端会造成utilization降低。如果能最后跑通,timing closure能过,也就算了。见过1:9,速度一般,5层金属,utilization依然可以做到~70%。
多说一句,如果综合不能做到meet setup并有一点裕量,这个样子没必要再往下走了,多半是浪费时间给后端挖坑。 我们的流程是综合必须满足setup,尤其是高速设计。达不到就打回去,RTL架构重做。
再多说一句,在CTS之前timing optimization是没有意义的。CTS之前跑timeDesign看看timing有什么变化是可以的,跑optDesign -drv也是合理的,跑optDesign -setup, optDesitgn -hold就多余了。
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