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请帮忙下载3篇IEEE论文:
X. Zhang and Z. Xie, “Efficient architectures for generalized integrated interleaved decoder,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 10, pp. 4018–4031, Oct. 2019.
W. Li, J. Lin, and Z. Wang, “A 124-Gb/s decoder for generalized integrated interleaved codes,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 8, pp. 3174–3187, Aug. 2019.
"Low-power partial-parallel Chien search architecture with polynomial degree reduction", Xinmiao Zhang;Itai Dror;Sanel Alterman 2016 IEEE International Symposium on Circuits and Systems (ISCAS) Year: 2016
谢谢!
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