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codes:makefile
run1:
vcs -sverilog -timescale=1ns/1ps po.v
run2:
vcs -sverilog -timescale=1ns/1ps po_bak.v
codes:po.v
module po;
class Packet;
int crc;
extern function int compute_crc();
endclass
function int Packet::compute_crc();
return 1;
endfunction
class MyPacket extends Packet;
extern function int compute_crc();
endclass
function int MyPacket::compute_crc();
return 0;
endfunction
function int crc(Packet pkt);
crc = pkt.compute_crc();
endfunction
initial begin
Packet p1=new();
MyPacket p2=new();
p1.crc=p1.compute_crc();
$display("p1.crc = %0d", p1.crc);
p2.crc = p2.compute_crc();
$display("p1.crc = %0d", p2.crc);
p1.crc = crc(p1);
$display("p1.crc = %0d", p1.crc);
p2.crc = crc(p2);
$display("p2.crc = %0d", p2.crc);
end
endmodule
codes:po_bak.v
module po_bak;
class Packet;
int crc;
extern virtual function int compute_crc();
endclass
function int Packet::compute_crc();
return 1;
endfunction
class MyPacket extends Packet;
extern virtual function int compute_crc();
endclass
function int MyPacket::compute_crc();
return 0;
endfunction
function int crc(Packet pkt);
crc = pkt.compute_crc();
endfunction
initial begin
Packet p1=new();
MyPacket p2=new();
p1.crc=p1.compute_crc();
$display("p1.crc = %0d", p1.crc);
p2.crc = p2.compute_crc();
$display("p1.crc = %0d", p2.crc);
p1.crc = crc(p1);
$display("p1.crc = %0d", p1.crc);
p2.crc = crc(p2);
$display("p2.crc = %0d", p2.crc);
end
endmodule
>make run1
p1.crc = 1
p2.crc = 0
p1.crc = 1
p2.crc = 1
>make run2
p1.crc = 1
p2.crc = 0
p1.crc = 1
p2.crc = 0
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