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本帖最后由 corinwjx 于 2021-4-2 05:38 编辑
大家好,我是刚接触UVM的新手,正在研究怎么配置virtual sequence和virtual sequencer,遇到了一些不太理解的问题。
仿真软件使用的是QuastaSim 10.4e (windows)
目前平台是这样配置的,在agent的build_phase中 create driver和sequencer,在connect_phase中完成port与export的连接,这一步没问题,在agent中就做这几件事。
在env中create出了agent和virtual sequencer,并且在connect_phase中把真sequencer的句柄与virtual sequencer的句柄相连。
在test中用config_db完成了default_sequence的配置,并且配置了sequence的几个参数。
在virtual sequence中采用手动启动sequence的方法,下面是body task的内容:
class my_virtual_sequence extends uvm_sequence;
`uvm_object_utils(my_virtual_sequence)
`uvm_declare_p_sequencer(my_virtual_sequencer)
function new(string name = "");
super.new(name);
endfunction //new()
my_sequence seq;
virtual task body();
if(starting_phase != null)
starting_phase.raise_objection(this);
seq = my_sequence::type_id::create("seq");
seq.start(p_sequencer.sequencer);
if(starting_phase != null)
starting_phase.drop_objection(this);
endtask
endclass //my_virtual_sequence extends uvm_sequence
我的真sequence中也是采用手动启动的方式:
task body;
int repeat_times;
int forced_value1;
int cnt = 0;
$display("my_sequence tries to get from %s", get_full_name());
if(!uvm_config_db #(int)::get(null, get_full_name(), "repeat_times", repeat_times))
begin
`uvm_error("my_sequence", "Failed to get repeat_times")
end
if(!uvm_config_db #(int)::get(null, get_full_name(), "forced_value1", forced_value1))
begin
`uvm_error("my_sequence", "Failed to get forced_value1")
end
forever begin
`uvm_info("my_sequence", "Entering the main loop", UVM_HIGH)
req = my_transaction::type_id::create("req");
`uvm_info("my_sequence", "Created req", UVM_HIGH)
start_item(req);
`uvm_info("my_sequence", "Item started", UVM_HIGH)
if (!req.randomize()) begin
`uvm_error("MY_SEQUENCE", "Randomize failed.");
end
req.data = forced_value1;
++cnt;
finish_item(req);
if(cnt > 2) break;
end
endtask: body
现在的问题是从输出的信息来看,sequence中直到`uvm_info("my_sequence", "Created req", UVM_HIGH)都是可以输出的,但是start_item(req)之后的内容全都没有,没有循环就直接仿真结束了。
这个是仿真输出的日志:
# UVM_INFO my_sequence.svh(33) @ 0: uvm_test_top.env.agent.sequencer@@seq [my_sequence] Entering the main loop
# UVM_INFO my_sequence.svh(35) @ 0: uvm_test_top.env.agent.sequencer@@seq [my_sequence] Created req
# UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 9
# UVM_WARNING : 1
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Questa UVM] 3
# [RNTST] 1
# [TEST_DONE] 1
# [This is new test] 1
# [UVM/RELNOTES] 1
# [UVMTOP] 1
# [my_sequence] 2
#
# ** Note: $finish : C:/questasim64_10.4e/win64/../verilog_src/uvm-1.2/src/base/
我理解的是sequence确实已经启动了,但是start_item那里跟什么机制发生了冲突。。。
请问这是什么原因造成的呢?另外《UVM实战》的6.3.5章节的代码,虽然用`uvm_do_on这些宏来实现,但也一样不能走完整个循环流程。
这里提前多谢指教了!
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