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本帖最后由 李默然 于 2023-5-21 17:48 编辑
工作地点：北京、上海、成都
职责描述：
Understand the architecture functional blocks being designed
Build C/C++/SystemC model for simulation
Compose test plan, verification vectors, functional cover groups to ensure functional completeness
Develop UVM/C++ test bench on both block level for test
Work with RTL designers to close all possible issues during implementation
Work closely with Vendors to mAIntain tools, flows and regression
任职要求：
Minimum MSEE/CE, or equivalent degree with at least 2 year of hands-on design verification experience in asic product development
Familiar with asic Frond-End implementation flow and hands-on experience in ASIC design verification
Experience with c/c++ programming skills is a plus
Experience with UVM methodology is a plus
Experience with SystemC and TLM will be strong advantage
Familiar with Unix/Linux , makefile and scripts (Ruby, Perl, Python etc.)
Strong problem solving skills, and attention to details
Good interpersonal skills (verbal and written)
A self-motivated team player
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发表于 2021-3-27 08:31:24
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