ADS2021Update2已发布，附官方下载链接

dongming

官方下载地址：
https://www.keysight.com/us/en/l ... ftware-2212036.html

主要更新：
数据显示窗口中可以插入图片，更新公式管理器功能。
DataLink更新到python3.8.5版本，包含pwdatatools可以更方便的导入各种文件格式的数据。

Design and Technology Management

• A new environment variable, EESOF_TEMP_PATH, can be used to specify the directory for the mini-dump file, the ADS AEL macro recording session file and a few other use cases in ADS platform.
• Unarchive command is improved to skip over any libraries that have problems, issue warnings for them, and proceed to completion.
  
• The message generated by TCL “puts” calls is displayed in ADS Message List pane where Error/Warning messages are typically shown.
• cds.lib file is supported for the workspace library definition. It can be enabled via setting the environment variable USE_CDS_LIB_WORKSPACE to a non-empty value.
  

Data Display

• Datalink is upgraded to use python 3.8.5 and contains the pwdatatools python package, a new beta feature, in its installation. For more information, see Using pwdatatools Python Package.
  
• Pictures can be inserted to a Data Display page as an image or an expression. For more information, see Pictures.
  
• Drag and drop operations can be performed from the Expression Manager to the Data Display page.
• DDS Palette is no longer locked to two columns and instead can be resized.
• The combo box for listing dataset is re-sizable.
  

Circuit Simulation

• General
  • Implemented BSIM-IMG Version 103.
    
  • Implemented HiCUM L2 Version 3.00.
  • Added support for string array MINT model parameter.
  • Simulated Annealing Corana optimizer on the schematic is now accessible.
  • Fixed an error when tuning with the SnP component using Spectre Nport file.
  • Unquoted expressions for parameters are now accepted when reading Hspice libraries.
  • Improved the gnode stepping and initial guess modes for Krylov solver.
    
    
  
  

• ElectroThermal
  • Support orthotropic conductivity where cross-plane k (k_z) exceeds in-plane k (k_xy), including for background layers.
    
  • ETH Transient: Store temperatures for entire devices (for example, transistor) derived from their sub-parts (for example, transistor fingers) in the dataset, that are back-annotated to the circuit simulator.
  • GUI to skip archive (.gda) file creation to save disk space.
  • Fix naming of temperature value (tval) file used in the original "Reuse Existing Temperature" feature.
    
  • Addressed the issue caused when saving a VAR item in the DC controller Output tab with ETH simulation.
    
    
  
  

HSD Design

• SerDes
  
  • ADS COM calculation supports COM Version 2.93.
  • ADS COM calculation supports Batch Simulation.
    
  • Smart eye probe supports eye mask measurement.
  • Improved S-Parameter Checker usability including easier port set up, NEXT, and FEXT measurements.
  • ADS FlexDCA probe supports differential signal from single-ended eye_probe for FlexDCA compliance test measurements.
  • Improved multi-lane Channel Sim Batch Simulation with an example.
    
  • Eye probe/Diff_Eye Probe component now recognizes PAM4_PRBS component in the name of VtPRBS source list for Transient Simulation.
    
• DDR/Memory
  
  • New Memory Interface AMI Model Builder for DDR5 and LPDDR5 AMI modeling in ADS.
    
  • Memory Designer now supports new DRAM type, GDDR6 solution.
    
  • Supports integrated IBIS-ISS (Interconnect SPICE Subcircuit) model in DDR Controller/Memory components.
    
  • Improved S-Parameter Checker usability including easier port set up, NEXT, and FEXT measurements.
    
  • Improved IBIS model editor grouping, that now allows you to add and remove signals from model group in DDR Controller/Memory.
    
  • Supports multi-threading in Memory Probe for speeding up measurements.
  • Facilitates easy access to the S-Parameter TDR Front Panelin DDR PCB.
  • Improved package model setup for touchstone file with header information, by automatic IBIS pin assignment.
  • Improved DIMM connector setup for touchstone file with header information, by automatic signal property assignment.
  • Memory Designer now supports any shape custom maskentry in Memory Probe.
  • Improved usability for Design Exploration, no need to use "Set" button to set the limits from the Memory probe dialog box.
    
  • Facilitates measurement names in dataset to be in same format as previous version (ADS 2021 Update 1.x and later) for an existing memory probe to support backward compatibility.
    
• EM-SIPro/PIPro
  • Faster mesh generation process for SIPro PA-SI simulations.
  • Automated mesh reuse feature for PA-SI, PI-AC, PI-DC, PI-TH and PI-ET simulations. Meshes are stored in cache in simulation directory and reused when possible.
  • Improved stability at low frequency for SIPro PA-SI simulations.
  • TDT plots with option to change rise time.
  • Capacitance to Ground in S-parameter plot.
  • Ability to parallelize PI-AC frequencies on single computer, or cluster.
  • Ability to delete cached model data for component models.
  • New DDR analysis with faster SI simulations as beta feature. Turn on beta functionality flag in SIPro Options to activate.
  • New SDS matrix solver as beta feature for PASI and PI-AC simulations, with improved performance in terms of memory and speed for larger systems.  Turn on beta functionality flag in SIPro Options to activate.
    
• Via Designer
  • Capacitance to Ground in S-parameter plot.
    
  
  

EM Simulation

• RFPro
  
  • Analyze the impact of conductor and dielectric layer thickness variations. For more information, see the Process Variation section in Create Full EM Extraction Analysis.
    
  • Bypass the upfront lengthy Green's function computation, aka substrate computation, by disabling the Green's function cache. The Green's functions will be computed during the frequency sweep what eliminates frequency interpolation errors. For more information, see Advanced Simulator Setup for Momentum RF and Microwave.
  • Opening an RFPro view no longer locks the layout view and the loading performance has been improved.
  • RFPro now supports the OpenAccess mustJoinTerms information and merges the terms based on their naming pattern. For example, 'C_1' and 'C_2' are merged into 'C'.
    
  • The Momentum Generation 2 via simplification is more robust.
  • The Momentum surface impedance model makes use of the global thickness estimation.
  • The Momentum preprocessor smoothens the sometimes noisy metal bias tables provided by foundry, leading to a more efficient mesh and improved simulation times.
  • The field visualization with a circuit excitation no longer locks the dataset.
  • The near field visualization provides a 'per-layer' filter.
  • Fixed the issue that custom addons did not automatically load at startup.
  • The Bulk Model option allows you to select how the device bulk connections are to be recognized and included in the simulation. For more information, see the Bulk Model section in Layout Options.
  • Capacitance to Ground in S-parameter plot.
    
• Substrate Editor
  
  • The following pilot feature simplifies the setup of (optionally stacked) thick conductors. Set SUBED_ENABLE_THICKCONDUCTOR=1 in the environment before launching ADS. You can now define a thick conductor between two substrate layer interfaces in the ADS substrate editor (.subst)
  • Fixed an issue where derived layers in ITF to LTD translation was incorrect for GF 12nm 3 plate MIM capacitor.
    
  
  

Power Electronics

• Power Electronics Model Builder tool enhancements:
  • Improved Measured Data validation and error reporting.
  • Improved usability in the way Data Display is used to plot and update measured data and simulation results.
  • Bugfixes related to launch of Data Display and use of Data Display template to plot the results.
    
• Surface Current Density visualization by layers in PEPro:
  • Added capability to view the Surface Current Density by layers in the Near Field results.
  • Fixed issues related to ASM HEMT symbol and updated the content.
    
  
  

Verification

Layout versus Layout Circuit Comparison

Layout versus Layout compares two versions of a layout and reports differences between the two layout views.

• LVL Circuit Comparison (ADS 2021 Update 2.0) reports missing components, differences in pin connections and parameter-value mismatches. LVL Circuit Comparison uses core technology in Layout versus Schematic (LVS) and requires the same configuration as LVS. Now you can browse to a layout view as well as a schematic.
• LVL Graphical Comparison is also supported (ADS 2021).
  

For more information, see Layout Versus Layout (LVL).

Layout Versus Schematic

LVS recognizes components with artwork "PyCell macro Pcell" as a device.

Design Rule Check

DRC displays poly area density target and actual values with increased precision.

Design Kits

• Added PDKV configuration to the kit.
• Fixed the PDK technology and the parameter callbacks to fix the PDKV reported issues
  

Virtual Test Bench (VTB)

• From ADS 2021:
  • Verification Test Bench (VTB) is now called Virtual Test Bench (VTB).
  • To install files that are required for the VTB functionality along with the ADS installer, you need to download a separate VTB installer for both Windows and Linux and manually install the VTB.
  • If you have already installed ADS and find VTB functionality is missing, then you need to download and manually install the VTB.
  • If you want to uninstall, then you need to manually uninstall VTB separately for both Windows and Linux.
    
  
  

chunhuic

有和谐文件吗

jacky33

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jacky33

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jacky33

thanks..............................................

jacky33

thanks......................................................................

jacky33

thanks................................................................................

jacky33

thanks................................................................................

jacky33

thanks................................................................................

jacky33

thanks................................................................................