【求助】我的状态机DC后不能工作，大家帮忙看看

jhm_seu

DC后，modelsim仿真显示next_state永远是x。
下面给出源代码。谢谢


`timescale 1ns/1ps
module AGU_RAM_READ(rst,clk,start,ram_cen,ram_wen,ram_oen,addr_ram,ram_read_done);
parameter  size = 10;
parameter  s_0 = 3'b000, s_1 = 3'b001, s_2 = 3'b011, s_3 = 3'b010, s_4 = 3'b110, s_5 = 3'b111;
input   rst,clk,start;
output   ram_cen,ram_wen,ram_oen;
output [size-1:0] addr_ram;
output   ram_read_done;
reg [2:0]  curr_state,next_state;
reg [1:0]  addr_h_2bit;
reg   sel_count;
reg [1:0]  sel_num;
reg   ram_cen;
wire   ram_wen,ram_oen;
wire [size-3:0] addr_count,addr_count_acc;
wire [1:0]  num,num_acc;
wire   ACC_8bit_carry,ACC_8bit_carry_reg;
wire   ram_read_done;
wire   acc_sel_din,sel_acc_8bit_carry;
assign addr_ram = {addr_h_2bit,addr_count};
assign ram_wen = 1'b1;
assign ram_oen = (curr_state == s_0)?1'b1:1'b0;
assign ram_read_done = ACC_8bit_carry_reg & (~addr_count[0]);
assign sel_acc_8bit_carry = (next_state == s_0)?1'b0:1'b1;

always @(posedge rst or posedge clk)
  if(rst) curr_state <= s_0;
  else  curr_state <= next_state;
  
always @(start or curr_state or num or ram_read_done)
  begin
    case(curr_state)
      s_0: begin
         sel_count = 1'b0; ram_cen = 1'b1;
         addr_h_2bit = 2'b00; sel_num = 2'b10;
         if(start)  next_state = s_1;
         else   next_state = s_0;
        end
      s_1: begin
         sel_count = 1'b0; ram_cen = 1'b0;
         addr_h_2bit = 2'b00; sel_num = 2'b00;
         if(ram_read_done) next_state = s_0;
         else   next_state = s_2;
        end
      s_2: begin
         sel_count = 1'b0; ram_cen = 1'b0;
         addr_h_2bit = 2'b10; sel_num = 2'b00;
         next_state = s_3;
        end
     s_3: begin
         sel_count = 1'b0; ram_cen = 1'b0;
         addr_h_2bit = 2'b01; sel_num = 2'b00;
         next_state = s_4;
        end
     s_4: begin
         sel_count = 1'b1; ram_cen = 1'b0;
         addr_h_2bit = 2'b11; sel_num = 2'b11;
         if(num[1] & (~num[0])) next_state = s_5;
         else   next_state = s_1;
        end
     s_5: begin
         sel_count = 1'b0; ram_cen = 1'b1;
         addr_h_2bit = 2'b11; sel_num = 2'b10;
         next_state = s_1;
        end  
     default: begin
         sel_count = 1'b0; ram_cen = 1'b1;
         addr_h_2bit = 2'b00; sel_num = 2'b00;
         next_state = s_0;
        end  
    endcase
  end
assign acc_sel_din = sel_acc_8bit_carry?ACC_8bit_carry:ACC_8bit_carry_reg;
dff_1 M0_ram_r_done(
   .clk(clk),
   .rst(rst),
   .in(acc_sel_din),
   .out(ACC_8bit_carry_reg)
  );
  
dff_2_sel M1_dff(
    .clk(clk),
    .rst(rst),
    .dff_cs(sel_num[1]),
    .sel(sel_num[0]),
    .din_a(num_acc),
    .din_b(2'b00),
    .dout(num)
   );
ACC_2bit M2_acc(
    .in(num),
    .out(num_acc)
   );
   
dff_8_cs M3_dff(
    .clk(clk),
    .rst(rst),
    .dff_cs(sel_count),
    .din(addr_count_acc),
    .dout(addr_count)
   );
   
ACC_8bit M4_acc(
    .in(addr_count),
    .out(addr_count_acc),
    .carry(ACC_8bit_carry)
   );
  
endmodule