芯原微电子(Verisilicon)招聘SOC验证工程师 (上海 & 南京）

liuxian · 发表于 2021-1-27 21:15:11

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本帖最后由 liuxian 于 2021-2-6 18:41 编辑

芯原微电子（Verisilicon)招聘SoC验证工程师 (上海 & 南京）
   内部推荐职位，非猎头, 各个level均有职位开放，感兴趣的朋友可以联系: peter_8410@163.com

   岗位要求等如下。另外soc design（上海 & 南京)也有职位开放，南京是新开的site, 其他职位如soc design, RF design, software development等均有职位，有朋友感兴趣的话也可以帮忙内推。

职位描述

understanding the exptected functionality of designs (IP/SoC)
Developing verification and regression plans
Designing and developing verification environment
Running RTL and gate level simulation/regression
Code/functional coverage development, analysis and closure

ְ职位要求

Master Degree, Minmum of 3 years design/verification experience(test plan, testbench, assertions, debugging designs, code/functional coverage etc.)
Knowledge in asic design process and verification tools/env (UVM)
Familiar with design and verification languages(verilog, System Verilog, SVA etc.)
Scripting and automation skills (tcl, perl, makefile, Python etc.) is a plus
Familiar with C/C++
Knowledge of DDR/Video/arm/USB/PCIE. Low power verification with UPF is a plus
Experience in cpu/dsp verification, including test plan and testbench development, test case development is a plus
Additional qualifications include: Good Ic verification skills and basic knowledge of logic or circuit desing, good communication and problem solving skills
Independent and self-managing