[ebook]SystemVerilog For Design 2nd

cfriend · 发表于 2007-12-5 18:32:59

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SystemVerilog For Design
Second Edition
A Guide to Using SystemVerilog for Hardware Design and Modeling
by
Stuart Sutherland
Simon Davidmann
Peter Flake

DownloadLink: http://rapidshare.com/files/74422601/springer_-_systemverilog_for_design__2nd_.pdf

batilin · 发表于 2008-4-14 11:54:23

well done, thanks.

snowinglyq · 发表于 2008-6-5 15:17:30

Thanks so much~!

pmsvq · 发表于 2008-11-1 16:53:31

多谢楼主共享。

ririyu · 发表于 2008-12-19 17:30:16

good!3ks!

jjw3310 · 发表于 2008-12-19 22:07:13

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nemolee · 发表于 2008-12-24 08:35:16

以下是從網路上擷取的內容簡介：

In its updated second edition, this book has been extensively revised on a chapter by chapter basis. The book accurately reflects the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter explaining the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.

這是一本不錯的書籍，可以讓我們了解SystemVerilog的語法使用

risccpu · 发表于 2008-12-24 18:17:33

good, 3x

mikeguan822 · 发表于 2009-8-3 09:45:43

thanks

rab2002 · 发表于 2009-11-13 00:03:43

可以看中文的啊

[ebook]SystemVerilog For Design 2nd

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

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