D触发器的HSPICE网表

ydb

有没有好心人，帮我看看这个D触发器的网表哪里有问题，求求了*AC Analysis for Dtrigger

.option post list

.global vdd gnd

.lib 'F:\rf018.l' TT

vdd   VDD  0 dc=1.8

vin1  D GND PULSE(0 1.8 0n 0n 0n 3n 6n)  
vin2  CLK GND PULSE(0 1.8 0n 0n 0n 1n 2n)  


.SUBCKT tg cn cp inout1 inout2 vdd vss
MNM0 inout1 cn inout2 vss nch W=1u L=0.18u m=1
MPM0 inout2 cp inout1 vdd pch W=4u L=0.18u m=1
.ENDS


.SUBCKT INV VDD VSS in out
MNM0 out in VSS VSS nch W=1u L=0.18u m=1
MPM0 out in VDD VDD pch W=4u L=0.18 m=1
.ENDS

XI3 CLK- CLK net13 Q- VDD GND tg
XI2 CLK CLK- net11 net15 VDD GND tg
XI1 CLK CLK- net12 net13 VDD GND tg
XI0 CLK- CLK D net11 VDD GND tg
XI9 VDD GND CLK- CLK INV
XI8 VDD GND CLK CLK- INV
XI7 VDD GND Q Q- INV
XI6 VDD GND net13 Q INV
XI5 VDD GND net12 net15 INV
XI4 VDD GND net11 net12 INV


.tran                0.001ns        30ns

.END

原理图如下；

bagshtag

XI9 VDD GND CLK- CLK INV
XI8 VDD GND CLK CLK- INV
What this is loop?

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The circuit is work

bagshtag

MPM0 out in VDD VDD pch W=4u L=0.18 m=1