always块对同一个reg进行赋值无法综合

lishuxuan · 发表于 2020-12-11 21:24:12

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module counter2(clk, rst, data_in, data_size, p2s_en, query_flag);

input clk;

input [63:0] data_in;

output [7:0] data_size;

output query_flag;

//reg [7:0] count;//2016.02.29

reg [7:0] data_size;

reg query_flag;

begin

//-----------------------------------------------------------------------------

always @(posedge clk or negedge rst)

if (!rst)

else if (data)

end

begin

p2s_en <= 1'b0;

m <= 0;

end

else if (flag)//2016.03.01

//if (flag && data[127])//2016.03.01

data_size <= 64-m;

if (data[63]==1 && data[62]==0 && data[61]==0 && data[60]==0)

query_flag <= 1'b1;

query_flag <= 1'b0;

else

data<= data<< 1;

end

//if (data[127]), then program will be a dead cycle. for example data[7:0]=8'b01001101.

//2015.04.02

/*

p2s_en <= 1'b1;

p2s_en <= 1'b0;

end

/* //ERROR: memory allocation failure

begin

p2s_en <= 1'b0;

m <= 0;

else

while (!data[127])

data <= data << 1;

end

p2s_en <= 1'b1;

query_flag <= 1'b1;

query_flag <= 1'b0;

end

endmodule

代码如上，quartus2报错，data_in有改变时，赋值给data，然后对data进行长度计算。请问如何修改代码才能变成可综合的

lishuxuan · 发表于 2020-12-11 21:29:33

`timescale 1ns/1ns
module counter2(clk, rst, data_in, data_size, p2s_en, query_flag);

  input clk;
  input rst;
  input [63:0] data_in;

  output [7:0] data_size;
  output p2s_en;
  output query_flag;


  reg [63:0] data;
  reg [7:0] data_size;
  reg p2s_en;
  reg query_flag;
  reg flag;

  integer m;

always @(data_in)
begin
   data = data_in;

end


  //-----------------------------------------------------------------------------

  always @(posedge clk or negedge rst)
begin
   if (!rst)
      flag <= 1'b0;
   else if (data)
      flag <= 1'b1;
end
  //-----------------------------------------------------------------------------

  always @(posedge clk or negedge rst)
begin
   if (!rst)
      begin
      data_size <= 8'b0;
      p2s_en <= 1'b0;
      query_flag <= 1'b0;
      m <= 0;

      end

   else if (flag)
      begin

      if (data[63])

         begin
            data_size <= 64-m;
            p2s_en <= 1'b1;
            if (data[63]==1 && data[62]==0 && data[61]==0 && data[60]==0)

            query_flag <= 1'b1;
            else
            query_flag <= 1'b0;
         end
      else
         begin
            data<= data<< 1;
            m <= m+1;
         end

      end
end



endmodule