Design and analysis of folded cascode OTAs using Gm-Id methodology based on flicker noise reduction

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Design and analysis of folded cascode OTAs using Gm/Id methodology based on flicker noise reduction                                   
Published: 17 April 2015

• Meysam Akbari,Omid Hashemipour
• Analog Integrated Circuits and Signal Processing  volume 83, pages343–352(2015)Cite this article                                                                                                        1452 Accesses
• 18 Citations
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Abstract: In this paper, a new methodology for design of folded cascode (FC) and recycling folded cascode (RFC) OTAs based on 1/f noise reduction is presented. With a new formulation for input referred flicker noise based on Gm/Id characteristic in all operation regions significantly enhance of the noise performance is achieved. Also, this technique leads to the larger DC gain and gain-bandwidth, and phase margin degeneration. The amplifiers were simulated in the 0.18 μm CMOS technology and the simulation results confirm the theoretical analyses. Proposed design methodology exhibits 50 % reduction of input voltage noise @ 1 Hz for RFC compared to the FC amplifier, without increasing the power consumption and silicon area.

https://link.springer.com/article/10.1007/s10470-015-0535-x

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