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发表于 2020-12-1 02:33:29
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本帖最后由 yaya126 于 2020-12-1 02:34 编辑
//--------------------------------------------------------------------------------------------
//
// Input file :
// Component name : dec_8b10b
// Author :
// Company :
//
// Description :
//
//
//--------------------------------------------------------------------------------------------
module dec_8b10b(RESET, RBYTECLK, AI, BI, CI, DI, EI, II, FI, GI, HI, JI, KO, HO, GO, FO, EO, DO, CO, BO, AO);
input RESET;
input RBYTECLK;
input AI;
input BI;
input CI;
input DI;
input EI;
input II;
input FI;
input GI;
input HI;
input JI;
output KO;
reg KO;
output HO;
reg HO;
output GO;
reg GO;
output FO;
reg FO;
output EO;
reg EO;
output DO;
reg DO;
output CO;
reg CO;
output BO;
reg BO;
output AO;
reg AO;
wire ANEB;
wire CNED;
wire EEI;
wire P13;
wire P22;
wire P31;
wire IKA;
wire IKB;
wire IKC;
wire XA;
wire XB;
wire XC;
wire XD;
wire XE;
wire OR121;
wire OR122;
wire OR123;
wire OR124;
wire OR125;
wire OR126;
wire OR127;
wire XF;
wire XG;
wire XH;
wire OR131;
wire OR132;
wire OR133;
wire OR134;
wire IOR134;
assign P13 = (ANEB & ((~CI) & (~DI))) | (CNED & ((~AI) & (~BI)));
assign P31 = (ANEB & CI & DI) | (CNED & AI & BI);
assign P22 = (AI & BI & ((~CI) & (~DI))) | (CI & DI & ((~AI) & (~BI))) | (ANEB & CNED);
assign ANEB = AI ^ BI;
assign CNED = CI ^ DI;
assign EEI = EI ~^ II;
assign IKA = (CI & DI & EI & II) | ((~CI) & (~DI) & (~EI) & (~II));
assign IKB = P13 & ((~EI) & II & GI & HI & JI);
assign IKC = P31 & (EI & (~II) & (~GI) & (~HI) & (~JI));
always @(posedge RESET or negedge RBYTECLK )
begin: KFN
if (RESET == 1'b1)
KO <= 1'b0;
else
KO <= IKA | IKB | IKC;
end
assign OR121 = (P22 & ((~AI) & (~CI) & EEI)) | (P13 & (~EI));
assign OR122 = (AI & BI & EI & II) | ((~CI) & (~DI) & (~EI) & (~II)) | (P31 & II);
assign OR123 = (P31 & II) | (P22 & BI & CI & EEI) | (P13 & DI & EI & II);
assign OR124 = (P22 & AI & CI & EEI) | (P13 & (~EI));
assign OR125 = (P13 & (~EI)) | ((~CI) & (~DI) & (~EI) & (~II)) | ((~AI) & (~BI) & (~EI) & (~II));
assign OR126 = (P22 & (~AI) & (~CI) & EEI) | (P13 & (~II));
assign OR127 = (P13 & DI & EI & II) | (P22 & (~BI) & (~CI) & EEI);
assign XA = OR127 | OR121 | OR122;
assign XB = OR122 | OR123 | OR124;
assign XC = OR121 | OR123 | OR125;
assign XD = OR122 | OR124 | OR127;
assign XE = OR125 | OR126 | OR127;
always @(posedge RESET or negedge RBYTECLK )
begin: DEC5B
if (RESET == 1'b1)
begin
AO <= 1'b0;
BO <= 1'b0;
CO <= 1'b0;
DO <= 1'b0;
EO <= 1'b0;
end
else
begin
AO <= XA ^ AI;
BO <= XB ^ BI;
CO <= XC ^ CI;
DO <= XD ^ DI;
EO <= XE ^ EI;
end
end
assign OR131 = (GI & HI & JI) | (FI & HI & JI) | (IOR134);
assign OR132 = (FI & GI & JI) | ((~FI) & (~GI) & (~HI)) | ((~FI) & (~GI) & HI & JI);
assign OR133 = ((~FI) & (~HI) & (~JI)) | (IOR134) | ((~GI) & (~HI) & (~JI));
assign OR134 = ((~GI) & (~HI) & (~JI)) | (FI & HI & JI) | (IOR134);
assign IOR134 = ((~(HI & JI))) & ((~((~HI) & (~JI)))) & ((~CI) & (~DI) & (~EI) & (~II));
assign XF = OR131 | OR132;
assign XG = OR132 | OR133;
assign XH = OR132 | OR134;
always @(posedge RESET or negedge RBYTECLK)
begin: DEC3B
if (RESET == 1'b1)
begin
FO <= 1'b0;
GO <= 1'b0;
HO <= 1'b0;
end
else
begin
FO <= XF ^ FI;
GO <= XG ^ GI;
HO <= XH ^ HI;
end
end
endmodule
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