uvm 编译报错问题

zhouyunlu · 发表于 2020-8-31 14:24:53

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ncvlog: *E,SVNOTY (../tb/tests/uart_seq_base.sv, 21|39): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`include file: (../tb/tests/uart_seq_base.sv line 21, file : ../tb/tests/uart_test_base.sv line 27)
`uvm_object_utils(uart_seq_base)

uart_seq_base中代码 21 行：class uart_seq_base extends uvm_sequence #(i_seq_item);

请问大佬们，这个错误可能是什么，找了很久没找到

boybeyond · 发表于 2020-8-31 18:40:03

可能是上一个文件缺了标点符号啥的，这个文件没有问题，那就是上一个文件的问题

A1985 · 发表于 2020-8-31 21:53:43

In SystemVerilog syntax, if a datatype begins with an identifier,
the identifier must refer to a type. Make sure that the typedef of the desired type
is visible in that scope or that there are not multiple wild card import clauses
importing typedefs of the same identifier name. The latter would make the use of
a simple type name ambiguous; in that case, in order to disambiguate which type is
desired you must provide a full type name of the form package_name::type_name.