上海天数智芯内部推荐--大量软件硬件职位

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外企文化没有996，薪资福利业界一流，著名大资本入场，原始股票…国内顶级GPGPU研发团队，感兴趣者请联系： guzhengfu@163.com  或微信：13072165417

（薪资面议）
1. 计算框架团队
1.1 工作内容
a. 基于自研 GPGPU 适配/优化/维护常用 AI 计算框架 TensorFlow、 PyTorch、 MXNet 等。
b. 实现易扩展、高性能、大规模的 AI 模型训练系统，发挥自研 GPGPU 的优越性。
c. 基于自研芯片设计构建高性能推理引擎。
1.2 资历要求
a. 计算机硕士+1 年相关工作经验，或计算机学士+3 年工作经验
b. 具有计算机相关领域背景，熟悉 AI 领域更好。
c. 熟练使用 Python/C/C++编程。
d. 熟悉 CUDA 编程。
e. 对 TensorFlow/PyTorch 实现原理熟悉、熟悉底层代码的实现。
f. 对分布式计算/训练框架有开发经验。
g. 熟悉 TensorRT/TVM 等推理引擎，了解原理。
h. 有良好的的团队合作精神和沟通能力
2. 函数库团队
2.1 工作内容
a. 为异构计算加速库编写 CUDA Kernel（如 BLAS, FFT, DNN andSparse）
b. 定义并实现加速库 API
c. 算法优化及性能调优
2.2 资历要求
a. 计算机硕士+1 年相关工作经验，或计算机学士+3 年工作经验
b. 熟悉 C/C++
c. 熟悉 CUDA Kernel 编程
d. 熟悉算法常用的基本数学原理
e. 熟悉 CPU/GPU 计算体系架构
f. 了解主流 AI 框架和 DNN 模型
g. 有良好的的团队合作精神和沟通能力

软件职位：（薪资面议）
3. 编译器团队
3.1 工作内容
a. 研发 CUDA 兼容的、基于 LLVM 的编译器
b. 实现与 CUDA PTX 指令兼容的编译器和运行环境
c. 测评和优化编译器的性能，为程序生成最优的机器指令
3.2 资历要求
a. 计算机硕士+1 年相关工作经验，或计算机学士+3 年工作经验
b. 熟悉 C/C++
c. 熟悉 CUDA 或 OpenCL
d. 熟悉 CPU/GPU 计算体系架构
e. 有 LLVM 工作经验者优先
f. 有在 CUDA PTX 上从事研发或了解 PTX 内部实现者优先
g. 有良好的的团队合作精神和沟通能力
4. 驱动团队
4.1 工作内容
a. 研发 GPGPU 用户态及内核态驱动
b. 协助性能团队分析并优化产品性能
c. 协助 DV，硬件团队完成产品定义以及芯片功能验证
d. 日常驱动维护以及 Debug
e. 内部测试及开发工具，以帮助完成芯片验证及后期 Debug
4.2 资历要求
a. 计算机硕士+1 年相关工作经验，或计算机学士+3 年工作经验
b. 熟悉 C/C++
c. 了解设备驱动开发， GPU 驱动经验尤佳
d. 熟悉操作系统架构(Linux/Unix/Windows)
e. 熟悉计算机体系结构
f. 有芯片 Bringup 项目经验者优先
g. 熟悉系统及驱动性能调优
h. 有良好的的团队合作精神和沟通能力

软件职位：（薪资面议）
5. 性能团队
5.1 工作内容
a. 对自研芯片的软件栈进行性能评价、分析
b. 定位性能问题，提供性能优化方案
c. 构建针对自研芯片系统软件栈的性能 Benchmark
d. 调研最新的性能相关开源技术，为后期的性能优化工作提供技术保障
e. 对市场上主流异构计算平台进行性能评价、分析和调研，对优化方法等进行技术储备
f. 基于自研芯片软件栈和 TVM 等开源项目，构建面向深度学习的推理加速引擎
g. GPU虚拟化相关性能调查及评价、分析
5.1 资历要求
a. 计算机硕士+1 年相关工作经验，或计算机学士+3 年工作经验
b. 熟悉 C/C++、 Python、 Shell 编程
c. 熟悉主流 AI 框架和 DNN 模型
d. 具有 Linux 及服务器性能相关工作经验
e. 具有异构性能优化经验
f. 熟悉 CUDA 者优先
g. 熟悉 LLVM/TVM 者优先
h. 有良好的的团队合作精神和沟通能力

硬件职位 （薪资面议）
1.Deep Learning Verification Engineer
Job Description
1.1Responsibilities:
a. Understand and closely discuss with architects /designers for hardware arch and micro-arch
b. Make up Block / IP / SOC level verification plan(methodology / testbench / testplan / coverage / ...)
and improve cross environment reuse
c. Develop and debug testbench, tests and driveverification closure with coverage and other sign-offs
d. Develop and verify reference C-model for functionaland performance purpose
e. Develop flows / tools to improve work efficiency
f. Communicate with software team for SW-HW interactionand code sharing
1.2 Qualifications:
a. Computer Science, Electrical Engineering,Micro-Electronics related majors are preferred
b. Good at Verilog/SystemVerilog/UVM/C/C++/Python
c. Good background in computer architecture is a plus
d. Familiarity with machine learning and deep learningis a plus
e. Familiarity with GPU computing (CUDA, OpenCL, cuDNN,TensorRT) is a plus
f. Good problem-solving ability is desired
g. Good communication skill is desired
h. Good team workingis desired
注：主要推荐方向 performance DV ， video DV， Memory DV

硬件职位 （薪资面议）
2.System Validation Engineer – PCIe
Job Description
2.1Resdonsibilities:
a. Working closely with IP design team to define PCIevalidation methodology;
b. Develop silicon level PCIe test plan, working withvalidation tools or test script to verify all PCIe
features
c. Attend ASIC bring-up and validation test, executeall PCIe feature test plans and track to be
successfully enabled;
d. To be responsible for system level issue debugging;
e. Develop automation tool/script to improve memorytest efficiency;
f. Provide technical support for both internal andexternal customers application
2.2 Qualifications:
a. Bachelor or Master in EE/CS or equivalent isrequired
b. Knowledge on PCI/PCI express architecture andhands-on experience with test equipment using
c. Familiar with high speed signal integrity theory andtest methodology;
d. Strong skills in system level issue debug andanalyzing
e. Experience in software development with scriptlanguages such as Perl, or Python;
f. A quick learner for new technologies and team player
注： core memory test 方向都需要
后端 team physical design engineer 也有需求
如有候选人可以找人事部门要 JD
上海市浦东新区亮秀路 112 号浦东软件园 Y2 座 202-204 室

3.ASIC Design Engineer
Job Description
3.1Job Responsibilities:
a. Develop micro-architecture, write micro-architecturespec and other documents
b. Write RTL code, meet the function target and have goodperformance/power/area efficiency
c. Apply low power, DFT, DFD and other digital designtechniques
d. Work with DV team to improve test plan and debugfailed tests
e. lean Lint, timing and other issues
f. Participate in silicon debugging
3.2 Qualifications::
a. Master in electrics or computer engineering.
b. Expert of Verilog RTL design
c. Experience of large digital ASIC project
d. Familiar with front-end EDA tools and flows
e. Programming skill in SystemVerilog, C/C++, perl,Tcl/tk, Python, etc. is preferred
f. Familiar with Linux Environment
g. Good communication in both Chinese and English
h. Good team player and strong sense of responsibility
i. Strong problem solving skills
j. Have one or some of the following design experience:memory controller, graphics, fabric,
microprocessor.
注： 最好为 memory 方向

硬件职位 （薪资面议）
4.StaffSOC Design Engineer (SCU HW – CPU direction)
Job Description
4.1Job Responsibilities:
a. Be responsible for block RTL code development andintegration for system control unit. Focus on
RISC-V ( or ARM CPU) IP integration and relatedsub-system blocks' coding;
b. Work with architect team (SOC/IP) to define blockfeature;
c. Work with SOC DV team to define the testplan;
d. Work with implementation team to close the timing;
e. Integrate block design into SOC;
f. Support silicon bringup.
4.2 Qualifications::
a. Be familiar with ASIC design flow and RTL coding, beable to do optimization for area, performance
and power;
b. Be familiar with system boot, power control andthermal control;
c. Be familiar with asynchronous design;
d. Be familiar with SOC architecture, has experience inthe protocol such as AXI, AHB or APB;
e. Be familiar with the external communicationinterface such as I2C, SPI, PCIe are plus;
f. Be familiar with the data transaction control suchas DMA is a plus;
g. Self-motivated, proactive, team work and achievementoriented;
h. Good communication skill and work well withcross-functional teams and technical leadership are
big plus.

硬件职位 （薪资面议）
5.DFTEngineer
Job Description
5.1Job Responsibilities:
a. The candidate is expected to be responsible forfollowing tasks:
b. Participate in SOC full Chip DFT feature andarchitecture definition
c. Implement SOC DFT function including SCAN, BoundarySCAN, MBIST, Analog Macro test logic
d. Generate DFT related timing constraints and work fortiming closure
e. Develop and verify high coverage and cost-effectivetest patterns for the production test 6. Evaluate
and establish the advanced DFT tools and flow
5.2 Qualifications::
a. 8+ years’s experience for Bachelor or 5+ years forMaster in DFT design and verification, test pattern
development
b. Good Knowledge of Scan/ATPG, MBIST and boundary scanand other DFT techniques
c. Good Knowledge of industry DFT tools like DFTMax,TetraMax ,TestKompress, FastScan, Tessent
Mbist, SMS etc
d. Good knowledge of digital SoC/ASIC design, includingSTA, verification and RTL coding
e. Proficient in hardware description languages such asVerilog, System Verilog and VHDL
f. Good Knowledge of script language, such as Tcl,Python, Perl
g. Good English communication skills
h. Strong commitment to schedule and work quality, goodteam player