tie—off cell

奋进2020

请问大佬们，tie-off cell 具体是个什么东西，后端小白只了解 tie-high和tie-low

samanji

https://www.edaboard.com/threads/whats-the-logical-tie-off-cells-in-soc-encounte.108904/
Tie-off cells provide ESD protected logic levels '1' and '0' to be used for connecting transistor gates.

the transistor gates in a design may be required to connect logic '1' and logic '0' permanently, ie VDD and VSS logic levels, It is usually tapped from near by Power lines.
But to ensure the Transistor gate recieves only ESD protected signal, the Tie-off cells are placed between these gates and power line.

These cells are part of standard cell library.soc encounter has the option for connecting Tie-off cells to the design.

奋进2020

samanji 发表于 2020-7-24 22:46
https://www.edaboard.com/threads/whats-the-logical-tie-off-cells-in-soc-encounte.108904/
Tie-off cel ...

thanks very much，best wish

zhaoyan0900

thanks