Job Description:
Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron chips for chip level design. The individual is expected to be an expert in multiple aspects in PD areas. The individual is also expected to be accountable for project delivery.
Job Requirement:
1. MSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASIC design
2. Experience in physical design of deep submicron digital ASIC chips
3. Hands on experience in large scale ASIC chip physical design
4. Knowledge in FinFET technology
5. Successfully gone through several complete product development cycles
6. Good listening, writing and speaking English
7. Good communication skills, strong interpersonal skills and the flexibility
8. Dedicated, hardworking and good team player
9. Power user of EDA tools from Synopsys (ICC/DC/PT/STAR-RC/RedHawk)
10. Familiar with Front-End EDA tools is a plus
11. Familiar with Unix/Linux environment and good at scripts