Modelsim5.6e的仿真库文件怎么生成，我搞了好几天都没弄出来，救命啊！

hs157

我的Modelsim5.6e启动时报出了下面的错误，从Xilinx下载的mxe5.6e_5.2isp3_simulation_libraries.zip解压到Modeltech_5.6e\目录下，并覆盖所有同名文件，仍然报同样的错误。我想问一下unisim等这些仿真库有什么简单的方法生成，谢谢先！
# ** Error: (vcom-19) Failed to access library 'unisim' at "unisim".
# No such file or directory. (errno = ENOENT)
# ERROR: cnt60.vhf(7): Library unisim not found.
# ERROR: cnt60.vhf(8): Unknown identifier: unisim
# ERROR: cnt60.vhf(11): VHDL Compiler exiting
# ERROR: D:/Modeltech_5.6e/win32/vcom failed.

bravelu

[这个贴子最后由bravelu在 2003/09/04 01:43am 第 1 次编辑]

如果不想知道太多信息可以直接看下一贴回复

ModelSim (MTI) - How do I compile the Xilinx SimPrim, LogiBLOX, and UniSim HDL libraries?
General Description:
For EE/PE, it is sometimes necessary to compile the HDL libraries before using them for design simulations. The advantages of the compiled approach are speed of execution and economy of memory. This answer record describes how to compile the various libraries.
NOTE: Do not compile the libraries for ModelSim XE, as they are precompiled. Please see (Xilinx Answer 10616) for more information.
Solution 1:

For the Xilinx 5.1i software:
In the 5.1i software, Xilinx provides an application called "COMPXLIB" that will specifically compile the HDL libraries for all Xilinx-supported simulators. (This replaces the TCL script that was used in previous versions of the software.)
Please note that "COMPXLIB" will not work on Linux until the 6.1i software release. For the 5.1i software, please use the following TCL script when running ModelSim on Linux:
ftp://ftp.xilinx.com/pub/swhelp/mti/xilinx_lib_5.zip
More information about using "COMPXLIB" is available in (Xilinx Answer 15338).
Solution 2:
For the Xilinx 4.1i/4.2i software:
A TCL script is available on the Xilinx FTP site. This script works with the EE/SE/PE versions of ModelSim.
NOTE: The TCL script does not compile the VHDL Smart Models.
PC:
ftp://ftp.xilinx.com/pub/swhelp/mti/xilinx_lib_4.zip
UNIX:
ftp://ftp.xilinx.com/pub/swhelp/mti/xilinx_lib_4.tar.gz
It is strongly recommended that you set the ModelSim environment variable prior to running the library compilation. The ModelSim environment variable is optional, and it instructs ModelSim to point to one master initialization file. If this option is not used, it is possible that the Xilinx library compilation information will be stored in a local initialization file that will not be seen by ModelSim the next time it is launched. If this happens, the Xilinx libraries will not be seen by the simulator, and the simulation will break. Set the environment variable as follows:
PC (Windows NT and 2000):
- Go to Start -> Settings -> Control Panel -> System -> Advanced -> Environment Variables.
- Click on the Add button in the System Variables section, and fill in the information as follows:
Variable Name: MODELSIM
Variable Value: Path to ModelSim directory/modelsim.ini (e.g., C:\Modeltech_5.5b\modelsim.ini)
Click "OK".
PC (Windows 98):
Add the following variable to the C:\autoexec.bat file:
set MODELSIM=<ath>
where <ath> is the path to the modelsim.ini file.
For example:
C:\modelsim_5.5b\modelsim.ini
Save and close the file, and restart the computer.
UNIX:
setenv MODELSIM /path_to_modelsim_install/modelsim.ini
FOR EE/SE:
Use the "source" command from the ModelSim prompt to load that TCL/TK code. At the ModelSim prompt, type:
MODELSIM> source <path_to_script>/xilinx_lib.tcl
FOR PE:
The flow for using the script in PE is different from the SE/EE flow. Follow the steps below to set up the script for MTI PE:
1. Prior to invoking ModelSim, set the environment variable "MODELSIM_TCL" to the location of the script.
(NOTE: MODELSIM_TCL can be a ":" -separated list of TCL/TK files to load.)
MODELSIM_TCL <path_to_script>/xilinx_lib.tcl
where <path_to_script> is the path name for the directory to where the script was saved.
2. Start ModelSim PE; the Xilinx Library Compile GUI will also appear.
NOTE: This script compiles all Xilinx simulation libraries. However, for Alliance, only the LogiBLOX, UniSim, XilinxCoreLib, and SimPrim libraries are supported. All other libraries are for use with Foundation ISE.
Solution 3:
Manually compiling the models:
ModelSim has extended the TCL language with simulation commands that allow TCL to be used as a scripting language for running ModelSim.
STEP 1:
These environment variable settings are provided for convenience; it is not necessary to type the full path every time. If you skip this step, simply type the full path in place of the "$" variables.
- Set access to the MODEL_TECH and XILINX environment variable:
set MODEL_TECH $env(MODEL_TECH)
set XILINX $env(XILINX)
- VERILOG_DESTN - Location for compiled Verilog libraries. This can be any directory you wish. (The provided path is recommended.) Make sure the directory exists before you proceed:
set VERILOG_DESTN [file join $MODEL_TECH/xilinx/verilog]
- VHDL_DESTN - Location for compiled VHDL libraries:
set VHDL_DESTN [file join $MODEL_TECH/xilinx/vhdl]
STEP 2:
If you would like logical library names to be available for all designs, set the MODELSIM environment variable to the location of your master .ini file.
For example:
setenv MODELSIM $MODEL_TECH/Xilinx/modelsim.ini
If MODELSIM is not set when VMAP is run, the logical library mapping is done locally; therefore, all VMAP commands would have to be run for each new HDL design.
STEP 3:
For Verilog users, the compilation commands that must be executed are:
SimPrim:
vlib $VERILOG_DESTN/simprims
vmap simprims_ver $VERILOG_DESTN/simprims
vlog -work simprims_ver $XILINX/verilog/src/simprims/*.v
LogiBLOX:
Uses the SimPrim-based library.
UniSim:
vlib $VERILOG_DESTN/uni3000
vmap uni3000 $VERILOG_DESTN/uni3000
vlog -work uni3000 $XILINX/verilog/src/uni3000/*.v
vlib $VERILOG_DESTN/unisims_ver
vmap unisims_ver $VERILOG_DESTN/unisims_ver
vlog -work unisims_ver $XILINX/verilog/src/unisims/*.v
vlib $VERILOG_DESTN/uni5200
vmap uni5200 $VERILOG_DESTN/uni5200
vlog -work uni5200 $XILINX/verilog/src/uni5200/*.v
vlib $VERILOG_DESTN/uni9000
vmap uni9000 $VERILOG_DESTN/uni9000
vlog -work uni9000 $XILINX/verilog/src/uni9000/*.v
CORE Generator:
Please see (Xilinx Answer 8066).
NOTE: To reference these libraries during Verilog simulation, the -L switch must be specified during VSIM execution to specify the library name given for the VMAP command.
Example for Verilog timing simulation:
vlog testbench.v time_sim.v glbl.v
vsim -L simprims_ver testbench_module_name glbl
Example for VHDL timing simulation:
SimPrim:
vlib $VHDL_DESTN/simprim
vmap simprim $VHDL_DESTN/simprim
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL.vhd
LogiBLOX:
vlib $VHDL_DESTN/logiblox
vmap logiblox $VHDL_DESTN/logiblox
vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/mvlutil.vhd
vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/mvlarith.vhd
vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/logiblox.vhd
UniSim (Versions A1.4 and later):
vlib $VHDL_DESTN/unisim
vmap unisim $VHDL_DESTN/unisim
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCFG4K.vhd
vlib $VHDL_DESTN/unisim_5k
vmap unisim_5k $VHDL_DESTN/unisim_5k
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCOMP52K.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL52K.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCFG52K.vhd
CORE Generator:
Please see (Xilinx Answer 8066).

bravelu

Xilinx Answer 15338 的内容相关部分看这里：

ModelSim PE (PC example)
This example compiles all of the libraries into the specified directory:
compxlib -s mti_pe -f all -l all -o c:\modeltech_5.6b\xilinx_libs
If multiple versions of ModelSim are installed, point to the desired executable directory:
compxlib -s mti_pe -f all -l all -o c:\modeltech_5.6b\xilinx_libs -p c:\Modeltech_5.6b\win32
自己替换一下安装路径。

palladium

我想问一下unisim等这些仿真库有什么简单的方法生成
老兄，我想你理解有误，unisim库是xilinx提供的，在其安装目录下
/xilinx/verilog/src/unisim.
你只需在第一次仿真你项目时把它编译进你的库中，以后就不用再编译了。

bravelu

我说的就是编译这些库的方法，我自己也喜欢用手工编译的，用那个编哪个，可能对于新手用批处理命令的可能好些。

szhjd

最简单的办法：
从XILINX下载相关的MXE库，解压缩到MODELSIM目录下（任意目录都可以，我一般是%MODELSIM%\xilinx）
然后在MODELSIM控制台下执行file\new\library，将相关库名和目录对应起来。
对了，做上面之前，必须将MODELSIM下的一个INI文件更改为可写的。做好之后可以打开这个文件看看内容，就明白是怎么回事情了，很明白的。

danielmann

手动编译vhdl库的顺序问题怎样解决？？？

bravelu

搞不清顺序就编译两次。

danielmann

两次好像也不行？？

bravelu

是有极少数几个东东编不好，不过基本用不到，没关系的。