【Paper】Design of Integrated Current Reference Circuits for a 180-nanometer BICMOS Silicon Process

kylinchan

Date of Graduation

5-2015

Document Type

Thesis

Degree Name

Bachelor of Science in Electrical Engineering

Degree Level

Undergraduate

Department

Electrical Engineering

Advisor/Mentor

Mantooth, Homer A

Abstract

The goal of this thesis is to provide design analysis, simulation results, and physical layout structure for three current references that are to be physically fabricated in a 180- nanometer BICMOS silicon process. The report briefly discusses the need for voltage and current references in Analog circuit applications, before zooming in to examine three topologies being tailored to the needs of an integrated solar micro-inverter system. These topologies are: proportional to absolute temperature (PTAT), complementary to absolute temperature (CTAT), and constant across temperature (Constant) bias circuits. First, each topology is designed schematically to meet the needs of the micro-inverter system. Those schematics are then taken in turn through simulations in Cadence virtuoso. These simulations return successful results showing functionality throughout temperature and power supply variation, as well as system startup. Finally, the circuits are laid out in Virtuoso’s layout package, utilizing common-centroid layout schemes and process parasitic simulations. The circuits are fully prepared for fabrication.

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