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[资料] 【Paper】Design of Integrated Current Reference Circuits for a 180-nanometer BICMOS Silicon Process

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发表于 2020-5-8 11:10:48 | 显示全部楼层 |阅读模式

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Date of Graduation
5-2015


Document Type
Thesis


Degree Name
Bachelor of Science in Electrical Engineering


Degree Level
Undergraduate


Department
Electrical Engineering


Advisor/Mentor
Mantooth, Homer A


Abstract
The goal of this thesis is to provide design analysis, simulation results, and physical layout structure for three current references that are to be physically fabricated in a 180- nanometer BICMOS silicon process. The report briefly discusses the need for voltage and current references in analog circuit applications, before zooming in to examine three topologies being tailored to the needs of an integrated solar micro-inverter system. These topologies are: proportional to absolute temperature (PTAT), complementary to absolute temperature (CTAT), and constant across temperature (Constant) bias circuits. First, each topology is designed schematically to meet the needs of the micro-inverter system. Those schematics are then taken in turn through simulations in Cadence Virtuoso. These simulations return successful results showing functionality throughout temperature and power supply variation, as well as system startup. Finally, the circuits are laid out in Virtuoso’s layout package, utilizing common-centroid layout schemes and process parasitic simulations. The circuits are fully prepared for fabrication.



toplayout.png

Design of Integrated Current Reference Circuits for a 180-nanomet.pdf

1.55 MB, 下载次数: 49 , 下载积分: 资产 -2 信元, 下载支出 2 信元

发表于 2020-5-8 14:37:11 | 显示全部楼层
发表于 2020-5-8 18:55:08 | 显示全部楼层
thanks
发表于 2020-5-9 12:21:59 | 显示全部楼层
Thanks
发表于 2020-11-10 20:05:01 | 显示全部楼层
thanks a lot
发表于 2020-11-11 00:16:51 | 显示全部楼层
Thanks!!!
发表于 2021-6-5 16:50:48 | 显示全部楼层
多谢分享
发表于 2021-6-5 20:42:55 | 显示全部楼层
aknakn
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