ebook：Writing Testbenches using System Verilog

ontheroad_m

High-level, abstract approach and guidelines for the *experienced* Verification engineer, March 24, 2007

By	hummingbird lover (California) - See all my reviews

The book's title is a bit misleading. It does NOT teach you Systemverilog (for Verification) -- there is a separate book by Chris Spear ("Systemverilog for Verification") sold by the same publisher that focuses more on Systemverilog syntax and language features. This book is NOT a tutorial (i.e. beginner's guide) on how to write testbenches -- although it does go through the basic concepts, objectives, and challenges in writing maintainable/re-usable testbench environments, most of the textbook examples are too cryptic/advanced for an entry-level engineer.

So then, what does this book focus on? Well, the book focuses on general guidelines to writing re-usuable, high-level testbenches. The author uses Systemverilog as the language to communicate his concepts, but as I said before, the book does NOT teach you Systemverilog. (To the author's credit, he is very upfront about that in foreward/intro section.)

Who should read it:
Experienced verification engineers with a basic understanding of Systemverilog (and why it's superior to Verilog), who want some ideas/examples of how to deploy Systemverilog's advanced features (like classes, structs, random vars) in a verification environment.

What I liked:
The use of classes to encapsulate bus-functional-models (BFMs), how to create and manage variations of a basic BFM (using extended/derived classes), etc. He also shows how to combine randomization with classes, to create random stimulus-sequences.

What could have been improved:
I was hoping the book would cover SVA (systemverilog assertions) in greater depth, but I guess there are other books for that. He also superficially mentions "configurations" -- that is a feature in Verilog-2001 and VHDL-93. The book should have covered that in more depth (even though it's not a new Systemverilog feature), as it pertains to testcase management and organization.

What you should have:
You need a good background and experience in ASIC/RTL-verification -- this book is not an introduction to testbench concepts, or the Systemverilog language! You need to know some Systemverilog language, so either have a different book (like Chris Spear's "Systemverilog for Verification"), or the official IEEE Systemverilog 1800-2005 LRM next to your side. Though not necessary, it's helpful to have a basic understanding about object-oriented programming, because the examples in the book use Systemverilog's classes (and inheritance) to illustrate a lot of points. Object-oriented concepts would otherwise be foreign to most engineers working in the hardware field.

Ohter notes:
The book makes numerous references to the VMM (Verilog Methodology Manual), which is a separate book by the same author. VMM is probably as close to a 'canned' (i.e. pre-built) testbench environment as you can get. If you run Synopsys VCS in your company, then VMM is worth investigatation. Unfortunately, I've heard it doesn't run well on competing simulators (Cadence, Mentor), as Systemverilog support is still in its infancy.

ma31360013

太好了，正是我要找的，谢

mingho

I like it.

fzfh1219

谢谢分享。。。。。

hudie2002

什么啊，根本就不全

slysysu

谢谢分享～～

newrfdesign

thanks