[招聘] 内部推荐soc设计和DFT工程师，待遇优厚，不可错过

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Staff SOC Design Engineer

RESPONSIBILITIES:

1. Be responsible for RTL code developmentof system control unit. Focus on one or multiple areas including: chip clk,reset, power control, fuse, thermal control, SOC low speed interface (GPIO,SPI, I2C, Uart etc);

2. Work with architect team (SOC/IP) todefine block feature;

3. Work with SOC DV team to define thetestplan;

4. Work with implementation team to closethe timing;

5. Integrate block design into SOC;

6. Support silicon bringup.

REQUIREMENTS:

1. Be familiar with ASIC design flow andRTL coding, be able to do optimization for area, performance and power;

2. Be familiar with asynchronous design;

3. Be familiar with SOC architecture, hasexperience in the protocol such as AXI, AHB or APB;

4. Be familiar with the analog design suchas GPIO, PLL or PVT sensors is a plus;

5. Be familiar with the externalcommunication interface such as I2C, SPI, UART. PCIE, USB or I2S are plus;

6. Be familiar with the data transactioncontrol such as DMA is a plus;

7. Self-motivated, proactive, team work andachievement oriented;

8. Good communication skill and work wellwith cross-functional teams and technical leadership are big plus.

DFT Engineer  

Job Description Responsibilities: 1. The candidate is expected to be responsible for following tasks:   2. Participate in SOC full Chip DFT feature and architecture definition  3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic  4. Generate DFT related timing constraints and work for timing closure  5. Develop and verify high coverage and cost-effective test patterns for the production test  6. Evaluate and establish the advanced DFT tools and flow    Qualifications:  1. 8+ years’s experience for Bachelor or 5+ years for Master in DFT design and verification, test pattern development  2. Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques   3. Good Knowledge of industry DFT tools like DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc  4. Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding  5. Proficient in hardware description languages such as Verilog, System Verilog and VHDL  6. Good Knowledge of script language, such as Tcl, Python, Perl   7. Good English communication skills  8. Strong commitment to schedule and work quality, good team player

上海张江职位，内部推荐，有意向的请搜索微信  5042029  添加，谢谢。