low power low voltage sigma-delta modulators in nanometer cmos

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low power low voltage sigma-delta modulators in nanometer cmos

List of Tables
List of Figures
Symbols and Abbreviations
Physical
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 ADCs in Nanometer CMOS Technologies 3
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4
2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 5
2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6
2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 6
2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9
2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10
2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13
2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
vii
2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . .

2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 17
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Principle of - ADC 19
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 24
3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33
3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
3.4.4 Performance Comparison of Traditional - Topologies . . 46
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
Level Approach 47
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54
4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55
4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66
4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76
4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76
4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87
4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88
4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System
Level Approach 99
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.2 The Full Feedforward - ADC Topology . . . . . . . . . . . . . . 100
5.2.1 Single-Loop Single-Bit Full Feedforward - Modulators . 101
5.2.2 Single-Loop Multibit Full Feedforward - Modulators . . 107
5.2.3 Cascaded Full Feedforward - Modulators . . . . . . . . . 110
5.2.4 Performance Comparison of Full Feedforward - Topologies 115
5.3 Linearity Analysis of -ADC . . . . . . . . . . . . . . . . . . . . 115
5.3.1 Non-Linearities Modeling in -ADC . . . . . . . . . . . . 116
5.3.2 Non-Linear OTA Gain Modeling in -ADC . . . . . . . . 117
5.3.3 Linearity Performance Comparison . . . . . . . . . . . . . . 117
5.4 Circuit Implementation of the Full Feedforward -
Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.5 A 1.8-V 2-MS/s - Modulator in 180-nm CMOS . . . . . . . . . . 124
5.5.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.5.2 Measurement results . . . . . . . . . . . . . . . . . . . . . . 131
5.6 A 1-V 1-MS/s - Modulator in 130-nm CMOS . . . . . . . . . . . 131
5.6.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.6.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 133
5.7 Multibit Full Feedforward -Modulator Design . . . . . . . . . . . 137
5.7.1 Optimized Loop Coefficients . . . . . . . . . . . . . . . . . . 138
5.7.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . 139
5.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

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baggio

网络问题，没发上去。。。
不好意思！！

baggio

网络问题，没发上去。。。
不好意思！！

ssdd_yy

xiexie !!

LAS.xs

ding!

LAS.xs

good!

kissshenzhu

thanks you

xiaoyingqun

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xitianzuo

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