内推：ARM中国深圳上海招聘CPU IP验证工程师

troyguo1234

邮箱: lunping.guo@armchina.com
CPU IP Verification Engineer
社招PD CPU全职Hardware Engineering
广东·深圳市北京市·海淀区上海市·闵行区


职位描述

The responsibilities of the roles include:

• Owning, planning, investigating, designing, or reviewing functional blocks to be composed into CPU IPs and their respective engineering methodologies such as models, designs, implementation, testbenches, test cases, formal properties, functional coverages, integrations, and flows in plans, specifications, or reports to meet requirements of architecture, product, technology, or engineering, to achieve quality and scalability goals
• Implementing, optimizing, validating, and debugging modules of models, designs, implementation, verification, validation, integration, or engineering flows in required programming languages, tools, and working environment according to corresponding plans, specs, methodologies, or quality process or signoff criterion, from inception to final quality of delivery
• Involvement in growth and development of the team, as well as team building, technology creation, profession development, engineering escalation, product sustaining, or customer support related activities, as well as others within company business scope
  

Additional responsibility for Senior and higher levels:

Working as a senior member in a team: plan, track, and delivering tasks, mentoring other engineers to ensure on-time delivery against plans, requirements, or specs

Additional responsibility for Staff or Principal levels:

• Participating in engineering feasibility analysis, review, and determination for requirements of market, product, architecture, technology, and engineering process
• Leading a team of engineers in various experience levels from project initiation to signoff, including goal setting, work planning, team building and mentoring, execution and delivery, risk management and customer engagement, as well as fulfilling overall requirements
• Build or development respective engineering team according to business need, including recruitment, team building, training, coaching, as well as inspiration, visioning, and career planning.
  

The essential skills or experiences include:

• Any experience in all functions of CPU, GPU, DSP, or similar processors projects with low-power and formal property assertion methodologies
• Proficiency in computer system architecture, SoC architecture, processor architecture, memory/bus architecture, and debug/trace architecture, or VLSI implementation technologies including low-power, customization, and embedded.
• Mastery of problem solving, technology innovation, engineer enablement, as well as teamwork scope negotiation and commitment
• Exposure to all stages of the engineering process from exploration and proof-of-concept, to delivery and maintenance
• Excellent communication and people skill in written and spoken English
• MSEE/CE/CS/Math related education
  

Additional essential qualification for Senior or higher levels:

• At least 8 years of experience in architecture analysis, micro-architecture, logic design or VLSI implementation, design verification, system validation, firmware programming, or digital design for comprehensive functional blocks with technologies such as computing, multimedia, or communication
• Proven delivery record in CPU or similar level of model, analysis, design, implementation, verification, or validation for program flows, memory flows, I/O flows, asynchronous event flows, compute pipes, as well as system, processor, and pipe controls, by using leading edge design, verification, and implementation flows and methodologies
  

Additional essential qualification for Staff or Principal levels:

• At least 15 or 20 years of experience in architecture analysis, micro-architecture, logic design or VLSI implementation, design verification, system validation, firmware programming, or digital design for comprehensive functional blocks with technologies such as computing, multimedia, or communication
• Expertise in architecture model, performance analysis, function pipelining/partition, advanced logic design, design verification, quality-of-result optimization, engineering workspace/workflow as well as ASIC implementation flows/tools and closure/signoff
• Technical leadership of complex engineering projects. Experience in all stages of the engineering process from exploration and proof-of-concept, to delivery and maintenance, with engineer mentoring, project managing, and requirement reasoning
• Knowledge in ASIC testability, test and product engineering, prototyping and system bringup, as well as related debugging activities
  

The desirable skills or experiences include:

• Exposure in performance analysis methodologies, design implementation methodologies, simulation verification methodologies, formal verification technologies, continuous integration and regression flow/tools, and verification coverage and signoff
• Knowledge in computing security architecture, parallel computing architecture, hardware reliability architecture, system application use cases, system application integration and programming, as well as system level debugging, benchmarking, and profiling
• Skillfulness in programming languages such as Verilog/SystemVerilog/SystemC, CPU assembly languages (preferably ARM), C/C++ languages, or Perl/TCL/Python scripts, XML/JSON markup languages, or other object-oriented or functional programming languages, as well as in EDA methodologies like UVM/OVM/VMM/LPM
• Experience of working cross sites in global teams
  

Additional desirable qualification for Senior or higher levels:

Participation in product marketing, technology research and proof-of-concept, customer engagement, product roadmap planning, and project planning

Proficiency in personal skills including communication, presentation, adjudication, negotiation, compromise, agreeability, and inspiration, as well as leadership to enable and escalate team members

Additional desirable qualification for Staff or Principal levels:

Capable of leading less-experienced engineers for solid quality of delivery signoff under a reasonable project plan

Capable of developing and ramping up less-experienced engineers for full engineering ownership during project execution under a reasonable project plan

职位信息

工作经验
3年 - 5年

troyguo1234

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