关于scan create_test_protocol无法覆盖分屏时钟的问题

vectorli

在做扫描链插入的时候，初始化配置如下，但是在做完下面的操作，执行dft_drc检查时，有上万个violation，是脚本写的不正确吗？还是遗漏了什么？
请大神们帮忙定位一下原因，非常感谢！！！！！！
read_file -format verilog {./DIG_ALL.v}
source -echo -verbose ./script/dc_setup.tcl
current_design DIG_ALL
link
source DIG_ALL.constraints.tcl
set_app_var test_default_delay 0
set_app_var test_default_bidir_delay 0
set_app_var test_default_strobe 40
set_app_var test_default_period 100
set_dft_signal -view existing_dft -internal_clocks multi -type ScanClock -port Scan_clk -timing [list 16.7 33.3]
set_dft_signal -view existing_dft -type TestMode -port TST_M -active_state 1
set_dft_signal -view existing_dft -type ScanEnable -port SCAN_SE -active_state 1
set_dft_signal -view spec -type ScanEnable -port SCAN_SE-active_state 1
set_dft_signal -view spec -type ScanDataIn -port SCAN_SI
set_dft_signal -view spec -type ScanDataOut -port SCAN_SO
set_dft_signal -view spec -type TestData -port  Scan_clk
create_test_protocol -infer_async -infer_clock
dft_drc
执行dft_drc后，有如下报告，是不是这些分屏时钟告警导致扫描链无法覆盖的问题？应该如何解决？
dc_shell> dft_drc
In mode: all_dft...
  Pre-DFT DRC enabled
Warning: A non-unate path in clock network for clock 'ext_clk1_div2'
from pin 'X10992/S' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'ext_clk1_div4'
from pin 'X10140/Z' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'ext_clk1_div8'
from pin 'X11010/S' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'ext_clk1_div16'
from pin 'X11001/S' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'ext_clk1_div32'
from pin 'X10991/S' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'ext_clk1_div512'
from pin 'X10178/Z' is detected. (TIM-052)
Information: Input delay ('fall') on clock port 'ext_clk0' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'ext_clk0' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('fall') on clock port 'ext_clk1' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'ext_clk1' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('fall') on clock port 'ext_clk0_div2' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'ext_clk0_div2' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('fall') on clock port 'ext_clk1_div2' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'ext_clk1_div2' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('fall') on clock port 'ext_clk1_div4' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'ext_clk1_div4' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('fall') on clock port 'ext_clk1_div8' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'ext_clk1_div8' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('fall') on clock port 'ext_clk1_div16' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'ext_clk1_div16' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('fall') on clock port 'ext_clk1_div32' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'ext_clk1_div32' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('fall') on clock port 'ext_clk1_div512' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'ext_clk1_div512' will be added to the clock's propagated skew. (TIM-112)

Information: Starting test design rule checking. (TEST-222)
  Loading test protocol
  ...basic checks...
  ...basic sequential cell checks...
      ...checking for scan equivalents...
  ...checking vector rules...
  ...checking pre-dft rules...

-----------------------------------------------------------------
Begin Pre-DFT violations...

Warning: Clock input CK of DFF X25995 was not controlled. (D1-1)
Information: There are 4505 other cells with the same violation. (TEST-171)
Warning: Set input SDN of DFF X24253 was not controlled. (D2-1)
Information: There are 51 other cells with the same violation. (TEST-171)
Warning: Reset input RDN of DFF X20054 was not controlled. (D3-1)
Information: There are 5425 other cells with the same violation. (TEST-171)
Warning: Clock input CK of DFF X11055 not active when clocks are set on. (D9-1)
Information: There are 1086 other cells with the same violation. (TEST-171)
Warning: Clock D2088 connects to data input (D) of DFF i_DIGFUNG_BLK/X20019. (D10-1)
Information: There are 36 other cells with the same violation. (TEST-171)
Warning: Clock T2001 can capture new data on TE input CK of DFF i_I2C_REG_BLK/X311. (D14-1)
         Source of violation: input CK of DFF i_I2C_REG_BLK/X20355.
Information: There are 7 other cells with the same violation. (TEST-171)
Warning: R3000 clock path affected by new capture on LS input RDN of DFF i_DIGFUNG_BLK/X21131. (D15-1)
         Source of violation: input RDN of DFF i_I2C_REG_BLK/X20366.
Information: There are 19 other cells with the same violation. (TEST-171)

Pre-DFT violations completed...
-----------------------------------------------------------------

-----------------------------------------------------------------
  DRC Report

  Total violations: 11136

-----------------------------------------------------------------

11136 PRE-DFT VIOLATIONS
  4506 Uncontrollable clock input of flip-flop violations (D1)
    52 DFF set/reset line not controlled violations (D2)
  5426 DFF set/reset line not controlled violations (D3)
  1087 Clock_port not active when clocks set to on violations (D9)
    37 Clock feeding data input violations (D10)
     8 Data path affected by clock captured by clock in trailing edge clock_port violations (D14)
    20 Clock path affected by clock captured by clock in level sensitive clock_port violations (D15)


Warning: Violations occurred during test design rule checking. (TEST-124)

-----------------------------------------------------------------
  Sequential Cell Report

  5801 out of 5865 sequential cells have violations

-----------------------------------------------------------------

SEQUENTIAL CELLS WITH VIOLATIONS
      *5704 cells have test design rule violations
      *  97 cells are clock gating cells
SEQUENTIAL CELLS WITHOUT VIOLATIONS
      *  64 cells are valid scan cells

ngohongtiep

you can use start_gui then debug it .
D1 : cause by missing clock define.
D2/D3 relative to mssing set/reset.

vectorli

ngohongtiep 发表于 2019-12-5 13:32
you can use start_gui then debug it .
D1 : cause by missing clock define.
D2/D3 relative to mssing s ...

我现在设置了一条如下命令，所有的触发器可以加入扫描链了，现在我有一个问题是想要部分触发器不加入到扫描链中，我应该如何设置？
set_dft_configuration -fix_clock enable -fix_set enable -fix_reset enable -fix_bus enable

ngohongtiep

you are using stupid command auto_fix will cause a lot of logic add-on. The idea is tracing on the GUI. for example : Warning: Clock input CK of DFF X25995 was not controlled. (D1-1)
Step 1 . Open GUI -> TEST -> run drc
Step 2. Click D1-1 trace back DFF.CK

vectorli

ngohongtiep 发表于 2019-12-5 23:00
you are using stupid command auto_fix will cause a lot of logic add-on. The idea is tracing on the G ...

X25995这个cell的CK是通过一个clockgate接入的，这是不是导致“Clock input CK of DFF X25995 was not controlled. (D1-1)“的原因？我应该如何解决这样的问题？

                               
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ngohongtiep

                               
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Trace back your clockgating.EN to the root . Good luck

vectorli

ngohongtiep 发表于 2019-12-6 21:08
Trace back your clockgating.EN to the root . Good luck

Warning: Clock input CK of DFF X25995 was not controlled. (D1-1)这个告警应该和和分屏时钟，虽然我通过命令set_dft_configuration -fix_clock enable，让所有的触发器都能加入扫描链中，但是现在问题来了，使用set_dft_configuration -fix_clock enable这条命令后，仿真就过不了了。大侠，应该怎么解决这样的问题啊？？