Verilog HDL A Guide to Digital Design and Synthesis, Second Edition.chm

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Title: Verilog HDL (2nd Edition) Author: Samir Palnitkar PublishDate: 2003-02-21 AddDate: 19000701 ISBN: 0130449113 EAN: 0076092024293 Publisher: Prentice Hall PTR
登录/注册后可看大图	登录/注册后可看大图			Description: Preface During my earliest experience with Verilog HDL, I waslookingfor a book that could give me a jump start on usingVerilog HDL. Iwanted to learn basic digital design paradigms and the necessaryVerilogHDL constructs that would help me build small digital circuits,usingVerilog and run simulations. After I had gained some experiencewith buildingbasic Verilog models, I wanted to learn to use Verilog HDLto build largerdesigns. At that time, I was searching for a book thatbroadly discussed advancedVerilog-based digital design concepts andreal digital design methodologies.Finally, when I had gained enoughexperience with digital design andverification of real IC chips, thoughmanuals of Verilog-based products wereavailable, from time to time, Ifelt the need for a Verilog HDL book that wouldact as a handyreference. A desire to fill this need led to the publication ofthefirst edition of this book. It has been more than six years since thepublication of thefirst edition. Many changes have occurred duringthese years. These years haveadded to the depth and richness of mydesign and verification experiencethrough the diverse variety of ASICand microprocessor projects that I havesuccessfully completed in thisduration. I have also seen state-of-the-artverification methodologiesand tools evolve to a high level of maturity. TheIEEE 1364-2001standard for Verilog HDL has been approved. The purpose of thissecondedition is to incorporate the IEEE 1364-2001 additions and introducetoVerilog users the latest advances in verification. I hope to makethis editiona richer learning experience for the reader. This bookemphasizes breadth rather than depth. The bookimparts to the reader aworking knowledge of a broad variety of Verilog-basedtopics, thusgiving the reader a global understanding of Verilog HDL-baseddesign.The book leaves the in-depth coverage of each topic to the VerilogHDLlanguage reference manual and the reference manuals of theindividualVerilog-based products. This book should be classified notonly as a Verilog HDLbook but, more generally, as a digital designbook. It is important to realizethat Verilog HDL is only a tool used indigital design. It is the means to anend-;the digital IC chip.Therefore, this book stresses the practicaldesign perspective more thanthe mere language aspects of Verilog HDL. WithHDL-based digital designhaving become a necessity, no digital designer canafford to ignoreHDLs. Who Should Use This Book The book is intended primarily forbeginners andintermediate-level Verilog users. However, for advancedVerilog users, thebroad coverage of topics makes it an excellentreference book to be used inconjunction with the manuals and trainingmaterials of Verilog-based products. The book presents a logicalprogression of Verilog HDL-basedtopics. It starts with the basics, suchas HDL-based design methodologies, andthen gradually builds on thebasics to eventually reach advanced topics, suchas PLI or logicsynthesis. Thus, the book is useful to Verilog users withvarying levelsof expertise as explained below. Students in logic design courses atuniversities Part 1 of this book is ideal for a foundationsemestercourse in Verilog HDL-based logic design. Students are exposedto hierarchicalmodeling concepts, basic Verilog constructs and modelingtechniques, and thenecessary knowledge to write small models and runsimulations. New Verilog users in the industry Companies are moving toVerilog HDL-based design. Part 1 ofthis book is a perfect jump startfor designers who want to orient their skillstoward HDL-based design.Users with basic Verilog knowledge who need to understand advancedconcepts Part 2 of this book discusses advanced concepts, such asUDPs,timing simulation, PLI, and logic synthesis, which are necessaryforgraduation from small Verilog models to larger designs. Verilogexperts All Verilog topics are covered, from the basicmodelingconstructs to advanced topics like PLIs, logic synthesis, andadvanced verificationtechniques. For Verilog experts, this book is ahandy reference to be usedalong with the IEEE Standard Verilog HardwareDescription Language referencemanual. The material in the booksometimes leans toward anApplication Specific Integrated Circuit (ASIC)design methodology. However, theconcepts explained in the book aregeneral enough to be applicable to thedesign of FPGAs, PALs, buses,boards, and systems. The book uses Medium ScaleIntegration (MSI) logicexamples to simplify discussion. The same conceptsapply to VLSIdesigns. How This Book Is Organized This book is organized into threeparts. Part 1, Basic Verilog Topics , covers all information that anewuser needs to build small Verilog models and run simulations. Note thatinPart 1, gate-level modeling is addressed before behavioral modeling.I havechosen to do so because I think that it is easier for a new userto see a 1-1correspondence between gate-level circuits and equivalentVerilog descriptions.Once gate-level modeling is understood, a new usercan move to higher levels ofabstraction, such as data flow modeling andbehavioral modeling, without losingsight of the fact that Verilog HDLis a language for digital design and is nota programming language.Thus, a new user starts off with the idea that Verilogis a language fordigital design. New users who start with behavioral modelingoften tendto write Verilog the way they write their C programs. Theysometimeslose sight of the fact that they are trying to representhardware circuits byusing Verilog. Part 1 contains nine chapters. Part2, Advanced Verilog Topics , contains the advancedconcepts a Veriloguser needs to know to graduate from small Verilog models tolargerdesigns. Advanced topics such as timing simulation,switch-levelmodeling, UDPs, PLI, logic synthesis, and advancedverification techniques arecovered. Part 2 contains six chapters. Part3, Appendices , contains information useful as areference. Usefulinformation, such as strength-level modeling, list of PLIroutines,formal syntax definition, Verilog tidbits, and large Verilog examplesisincluded. Part 3 contains six appendices.

chocobocn

c 新帖都没有人看呀

象眼

呵呵，这么好的东西需要顶啊

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pkuz

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wojiushiwo1989

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xxxyyy114

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jackiedepp

非常感谢

netking

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