vcs2017.12

gobar25 · 发表于 2021-8-14 19:00:24

part 35

gobar25 · 发表于 2021-8-14 19:09:29

part 36

gobar25 · 发表于 2021-8-14 19:18:29

part 37

gobar25 · 发表于 2021-8-14 19:24:30

part 37

gobar25 · 发表于 2021-8-14 19:27:40

part 37

gobar25 · 发表于 2021-8-14 19:33:41

part 36

gobar25 · 发表于 2021-8-17 18:22:08

n compilation using vcs  i get the following error with VCS MX 2017.12 but i get no error in vcsMX 2014.03

vcs -full64 -sverilog compare.sv compare_tb.sv
                     Chronologic VCS (TM)
   Version N-2017.12-SP2_Full64 -- Tue Aug 17 15:01:09 2021
            Copyright (c) 1991-2017 by Synopsys Inc.
                     ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'compare.sv'
Parsing design file 'compare_tb.sv'
Top Level Modules:
   compare
   compare_tb
No TimeScale specified
Starting vcs inline pass...

2 modules and 0 UDP read.
recompiling module compare
recompiling module compare_tb
Both modules done.
/usr/bin/ld: rmapats_mop.o: .symtab local symbol at index 8 (>= sh_info of 1)
/usr/bin/ld: rmapats_mop.o: error adding symbols: bad value
collect2: error: ld returned 1 exit status
make: *** [Makefile.hsopt:47: rmapats.so] Error 1
Error: Failed to make rmapats.so @ simv.daidir/rmapats.so

gobar25 · 发表于 2021-8-22 00:06:01

anybody can help with the above problem (in english ) ???

gobar25 · 发表于 2021-9-5 00:42:28

On compilation using vcs  i get the following error with VCS MX 2017.12 but i get no error in vcsMX 2014.03

vcs -full64 -sverilog compare.sv compare_tb.sv
                     Chronologic VCS (TM)
   Version N-2017.12-SP2_Full64 -- Tue Aug 17 15:01:09 2021
            Copyright (c) 1991-2017 by Synopsys Inc.
                     ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'compare.sv'
Parsing design file 'compare_tb.sv'
Top Level Modules:
   compare
   compare_tb
No TimeScale specified
Starting vcs inline pass...

2 modules and 0 UDP read.
recompiling module compare
recompiling module compare_tb
Both modules done.
/usr/bin/ld: rmapats_mop.o: .symtab local symbol at index 8 (>= sh_info of 1)
/usr/bin/ld: rmapats_mop.o: error adding symbols: bad value
collect2: error: ld returned 1 exit status
make: *** [Makefile.hsopt:47: rmapats.so] Error 1
Error: Failed to make rmapats.so @ simv.daidir/rmapats.so

zyfwh · 发表于 2021-9-5 16:33:16

非常感谢提供

vcs2017.12

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